A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL - researchr publication

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Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida. A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. J. Solid-State Circuits, 30(11):1189-1195, November 1995. [doi]

Abstract is missing.

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