The following publications are possibly variants of this publication:
- A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/OKazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto. jssc, 32(11):1758-1765, 1997. [doi]
- A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiersKoichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida. jssc, 30(4):480-486, April 1995. [doi]
- A 6-ns, 1.5-V, 4-Mb BiCMOS SRAMHideo Toyoshima, Shigeru Kuhara, Koichi Takeda 0001, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki. jssc, 31(11):1610-1617, 1996. [doi]