Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah. Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(11):2376-2392, 2006. [doi]

@article{JessKNOV06,
  title = {Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits},
  author = {Jochen A. G. Jess and K. Kalafala and Srinath R. Naidu and Ralph H. J. M. Otten and Chandramouli Visweswariah},
  year = {2006},
  doi = {10.1109/TCAD.2006.881332},
  url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2006.881332},
  researchr = {https://researchr.org/publication/JessKNOV06},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {25},
  number = {11},
  pages = {2376-2392},
}