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Li Jiang, Lin Huang, Qiang Xu. Test architecture design and optimization for three-dimensional SoCs. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 220-225, IEEE, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraintLi Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak. iccad 2009: 191-196 [doi] Reconfigured test architecture optimization for TSV-based three-dimensional SoCsKele Shen, Dong Xiang, Zhou Jiang. ieiceee, 11(16):20140661, 2014. [doi]
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