A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology

John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis. A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology. TRETS, 17(1), March 2024. [doi]

Abstract

Abstract is missing.