Noise-aware interconnect power optimization in domino logic synthesis - researchr publication related

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Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang. Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. VLSI Syst., 11(1):79-89, 2003. [doi]

The following publications are possibly variants of this publication:

Noise constrained power optimization for dual VT domino logicSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. iscas 2001: 158-161 [doi]

Noise constrained transistor sizing and power optimization for dual Vs::t:: domino logicSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. tvlsi, 10(5):532-541, 2002. [doi]

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power ConstrainSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. date 2002: 260-267 [doi]

Crosstalk-aware domino logic synthesisYi-Yu Liu, TingTing Hwang. date 2006: 1312-1317 [doi]

Crosstalk-Aware Domino-Logic SynthesisYi-Yu Liu, TingTing Hwang. tcad, 26(6):1155-1161, 2007. [doi]

Coupling-aware minimum delay optimization for domino logic circuitsKi-Wook Kim, Seong-Ook Jung, Sung-Mo Kang. iscas 2001: 371-374 [doi]

Noise-aware power optimization for on-chip interconnectKi-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang. islped 2000: 108-113 [doi]

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