The following publications are possibly variants of this publication:
- Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICsMasaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. ats 2013: 13-18 [doi]
- A built-in supply current test circuit for electrical interconnect tests of 3D ICsMasaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. 3dic 2014: 1-6 [doi]
- A built-in test circuit for open defects at interconnects between dies in 3D ICsWidianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume. 3dic 2012: 1-5 [doi]
- A Design for Testability of Open Defects at Interconnects in 3D Stacked ICsFara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth. ieicet, 101-D(8):2053-2063, 2018. [doi]
- CMOS open defect detection by supply current testMasaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada. date 2001: 509 [doi]