Yifang Liu, Jiang Hu, Weiping Shi. Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(12):2183-2196, 2008. [doi]
@article{LiuHS08:4,
title = {Buffering Interconnect for Multicore Processor Designs},
author = {Yifang Liu and Jiang Hu and Weiping Shi},
year = {2008},
doi = {10.1109/TCAD.2008.2006149},
url = {http://dx.doi.org/10.1109/TCAD.2008.2006149},
researchr = {https://researchr.org/publication/LiuHS08%3A4},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {27},
number = {12},
pages = {2183-2196},
}