The following publications are possibly variants of this publication:
- Yield-award placement optimization for Switched-Capacitor analog integrated circuitsChien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey. socc 2011: 170-173 [doi]
- Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated CircuitsJwu-E Chen, Pei-Wen Luo, Chin-Long Wey. tcad, 29(2):313-318, 2010. [doi]
- Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated CircuitsCheng-Ping Wang, Chin-Long Wey. iccd 1997: 468-473
- Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated CircuitsPei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu. tcad, 27(11):2097-2101, 2008. [doi]