John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. J. Solid-State Circuits, 38(11):1795-1803, 2003. [doi]
@article{ManeatisKMMS03-0,
title = {Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL},
author = {John G. Maneatis and Jaeha Kim and Iain McClatchie and Jay Maxey and Manjusha Shankaradas},
year = {2003},
doi = {10.1109/JSSC.2003.818298},
url = {https://doi.org/10.1109/JSSC.2003.818298},
researchr = {https://researchr.org/publication/ManeatisKMMS03-0},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {38},
number = {11},
pages = {1795-1803},
}