Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL - researchr publication references

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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. J. Solid-State Circuits, 38(11):1795-1803, 2003. [doi]

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