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Peichen Pan, C. L. Liu. Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst., 3(3):437-462, 1998. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Optimal Clock Period FPGA Technology Mapping for Sequential CircuitsPeichen Pan, C. L. Liu. dac 1996: 720-725 [doi] Technology Mapping of Sequential Circuits for LUT-Based FPGAs for PerformancePeichen Pan, C. L. Liu. fpga 1996: 58-64 [doi] Optimal clock period clustering for sequential circuits with retimingPeichen Pan, Arvind K. Karandikar, C. L. Liu. tcad, 17(6):489-498, 1998. [doi] Optimal Clock Period Clustering for Sequential Circuits with RetimingArvind K. Karandikar, Peichen Pan, C. L. Liu. iccd 1997: 122-127
The following publications are possibly variants of this publication: