The following publications are possibly variants of this publication:
- Compressor tree synthesis on commercial high-performance FPGAsHadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne. trets, 4(4):39, 2011. [doi]
- Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAsAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne. fpga 2008: 181-190 [doi]
- Improving Synthesis of Compressor Trees on FPGAs via Integer Linear ProgrammingHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. date 2008: 1256-1261 [doi]
- Automatic synthesis of compressor trees: reevaluating large countersAjay K. Verma, Paolo Ienne. date 2007: 443-448 [doi]
- Exploiting fast carry-chains of FPGAs for designing compressor treesHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. fpl 2009: 242-249 [doi]
- Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAsAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne. trets, 2(2), 2009. [doi]
- Approximate Adder Tree Synthesis for FPGAsSina Boroumand, Philip Brisk. reconfig 2019: 1-8 [doi]