State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. In VLSI Design. pages 15-20, 1993.

Authors

Rubin A. Parekhji

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G. Venkatesh

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Sunil D. Sherlekar

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