Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. In VLSI Design. pages 15-20, 1993.
@inproceedings{ParekhjiVS93,
title = {State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits},
author = {Rubin A. Parekhji and G. Venkatesh and Sunil D. Sherlekar},
year = {1993},
tags = {design},
researchr = {https://researchr.org/publication/ParekhjiVS93},
cites = {0},
citedby = {0},
pages = {15-20},
booktitle = {VLSI Design},
}