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Dongmin Park, SeongHwan Cho. A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. J. Solid-State Circuits, 47(12):2989-2998, 2012. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOSDongmin Park, SeongHwan Cho. isscc 2012: 344-346 [doi] A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integratorsJae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(4):918-925, 2005. [doi] A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOSWoojae Lee, SeongHwan Cho. iscas 2010: 1328-1331 [doi]
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