The following publications are possibly variants of this publication:
- Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit SynthesisHuiying Yang, Ranga Vemuri. vlsid 2007: 201-206 [doi]
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- Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog CircuitsAlmitra Pradhan, Ranga Vemuri. vlsid 2009: 131-136 [doi]
- A high level language for pre-layout extraction in parasite-aware analog circuit synthesisRaoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri. glvlsi 2004: 271-276 [doi]