A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS - researchr publication related

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Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Huang, Afshin Momtaz, Jun Cao. A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 32-33, IEEE, 2013. [doi]

The following publications are possibly variants of this publication:

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOSBharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao. jssc, 48(12):3219-3228, 2013. [doi]

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A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technologyKe Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang. cicc 2015: 1-4 [doi]

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