The following publications are possibly variants of this publication:
- Hierarchical Identification of Untestable Faults in Sequential CircuitsJaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus. dsdm 2007: 668-671 [doi]
- Untestable Fault Identification in Sequential Circuits Using Model-CheckingJaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko. ats 2008: 21-26 [doi]
- Identifying Untestable Faults in Sequential Circuits Using Test Path ConstraintsTaavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara. et, 28(4):511-521, 2012. [doi]
- FPGA-based fault emulation of synchronous sequential circuitsPeeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar. iet-cdt, 1(2):70-76, 2007. [doi]