On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout - researchr publication related

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Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita. On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. In Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002. pages 83-89, IEEE Computer Society, 2002. [doi]

The following publications are possibly variants of this publication:

Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic CircuitsSudhakar M. Reddy, Madhukar K. Reddy. TC, 35(8):742-754, 1986.

On Synthesis-for-Testability of Combinational Logic CircuitsIrith Pomeranz, Sudhakar M. Reddy. dac 1995: 126-132 [doi]

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic CircuitsIrith Pomeranz, Sudhakar M. Reddy. TC, 45(1):50-62, 1996.

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