A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora. A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. J. Solid-State Circuits, 42(1):17-25, 2007. [doi]

This author has not been identified. Look up 'Stefan Rusu' in GoogleThis author has not been identified. Look up 'Simon M. Tam' in GoogleThis author has not been identified. Look up 'Harry Muljono' in GoogleThis author has not been identified. Look up 'David Ayers' in GoogleThis author has not been identified. Look up 'Jonathan Chang' in GoogleThis author has not been identified. Look up 'Brian S. Cherkauer' in GoogleThis author has not been identified. Look up 'Jason Stinson' in GoogleThis author has not been identified. Look up 'John Benoit' in GoogleThis author has not been identified. Look up 'Raj Varada' in GoogleThis author has not been identified. Look up 'Justin Leung' in GoogleThis author has not been identified. Look up 'Rahul Dilip Limaye' in GoogleThis author has not been identified. Look up 'Sujal Vora' in Google

runs on WebDSL