Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora. A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. J. Solid-State Circuits, 42(1):17-25, 2007. [doi]
@article{RusuTMACCSBVLLV07,
title = {A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache},
author = {Stefan Rusu and Simon M. Tam and Harry Muljono and David Ayers and Jonathan Chang and Brian S. Cherkauer and Jason Stinson and John Benoit and Raj Varada and Justin Leung and Rahul Dilip Limaye and Sujal Vora},
year = {2007},
doi = {10.1109/JSSC.2006.885041},
url = {https://doi.org/10.1109/JSSC.2006.885041},
researchr = {https://researchr.org/publication/RusuTMACCSBVLLV07},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {42},
number = {1},
pages = {17-25},
}