The following publications are possibly variants of this publication:
- A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms ErrorQixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx. isscc 2019: 408-410 [doi]
- 9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLLNereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx. isscc 2016: 176-177 [doi]
- A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS ProcessYupeng Fu, Lianming Li, Yilong Liao, Xuan Wang, Yongjian Shi, Dongming Wang 0002. tvlsi, 28(7):1600-1609, 2020. [doi]
- A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-BandwidthPratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx. jssc, 55(12):3294-3307, 2020. [doi]
- 17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp BandwidthPratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx. isscc 2020: 278-280 [doi]