Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation - researchr publication related

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Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal. Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 88-94, IEEE Computer Society, 1997. [doi]

The following publications are possibly variants of this publication:

Design for Testability for Path Delay faults in Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. dac 1993: 453-457 [doi]

On test coverage of path delay faultsAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal. vlsid 1996: 418-421 [doi]

Effective Path Selection for Delay Fault Testing of Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal. itc 1997: 998-1003

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