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Naofumi Takagi, Shuzo Yajima. On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic. IEEE Transactions on Computers, 36(11):1310-1317, 1987.
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design of high speed MOS multiplier and divider using redundant binary representationShigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi. arith 1987: 80-86 [doi] An on-line error-detectable array divider with a redundant binary representation and a residue codeNaofumi Takagi, Shuzo Yajima. ftcs 1988: 174-179 [doi]
The following publications are possibly variants of this publication: