Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement - researchr publication related

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Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee. Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Transactions, 94-A(2):706-716, 2011. [doi]

The following publications are possibly variants of this publication:

Double-via insertion enhanced X-architecture clock routing for reliabilityChia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee. iscas 2010: 3413-3416 [doi]

Post-routing redundant via insertion for yield/reliability improvementKuang-Yao Lee, Ting-Chi Wang. aspdac 2006: 303-308 [doi]

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay considerationChung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee. integration, 44(1):87-101, 2011. [doi]

Optimal post-routing redundant via insertionKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao. ispd 2008: 111-117 [doi]

A yield improvement methodology using pre- and post-silicon statistical clock schedulingJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. iccad 2004: 611-618 [doi]

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