The following publications are possibly variants of this publication:
- Synthesis of nonzero clock skew circuitsShih-Hsu Huang, Yow-Tyng Nieh. tcad, 25(6):961-976, 2006. [doi]
- Clock Period Minimization of Non-Zero Clock Skew CircuitsShih-Hsu Huang, Yow-Tyng Nieh. iccad 2003: 809-812 [doi]
- Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current MinimizationShih-Hsu Huang, Chun-Hua Cheng. jise, 26(6):2249-2266, 2010. [doi]
- High-Level Synthesis for Minimum-Area Low-Power Clock GatingShih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li. jise, 28(5):971-988, 2012. [doi]
- Clock Period Minimization with Minimum Leakage PowerShih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh. todaes, 21(1):9, 2015. [doi]
- Minimum Inserted Buffers for Clock Period MinimizationShih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang. jise, 27(5):1513-1526, 2011. [doi]
- Clock Period Minimization with Minimum Delay InsertionShih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh. dac 2007: 970-975 [doi]