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Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson. Reversible-logic design with online testability. IEEE T. Instrumentation and Measurement, 55(2):406-414, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Online Testable Reversible Logic Circuit Design using NAND BlocksD. P. Vasudevan, Parag K. Lala, James Patrick Parkerson. dft 2004: 324-331 [doi] CMOS Realization of Online Testable Reversible Logic GatesD. P. Vasudevan, Parag K. Lala, James Patrick Parkerson. isvlsi 2005: 309-310 [doi]
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