The following publications are possibly variants of this publication:
- On Modulo 2^n+1 Adder DesignHaridimos T. Vergos, Giorgos Dimitrakopoulos. TC, 61(2):173-186, 2012. [doi]
- New architectures for modulo 2N - 1 addersGiorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou. icecsys 2005: 1-4 [doi]
- Fast Parallel-Prefix Modulo 2^n+1 AddersCostas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos. TC, 53(9):1211-1216, 2004. [doi]
- Diminished-One Modulo 2:::n:::+1 Adder DesignHaridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos. TC, 51(12):1389-1399, 2002. [doi]
- Fast modulo 2:::n:::+1 multi-operand adders and residue generatorsHaridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou. integration, 43(1):42-48, 2010. [doi]
- Design of efficient modulo 2:::n:::+1 multipliersHaridimos T. Vergos, Costas Efstathiou. iet-cdt, 1(1):49-57, 2007. [doi]
- Efficient modulo 2:::n:::±1 squarersDimitris Bakalis, Haridimos T. Vergos, A. Spyrou. integration, 44(3):163-174, 2011. [doi]
- Efficient Diminished-1 Modulo 2^n+1 MultipliersCostas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos. TC, 54(4):491-496, 2005. [doi]
- A Family of Area-Time Efficient Modulo 2n+1 AddersHaridimos T. Vergos. isvlsi 2010: 442-443 [doi]