An automorphic approach to verification pattern generation for SoC design verification using port-order fault model

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems, 21(10):1225-1232, 2002. [doi]

Authors

Chun-Yao Wang

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Shing-Wu Tung

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Jing-Yang Jou

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