Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems, 21(10):1225-1232, 2002. [doi]
@article{WangTJ02a,
title = {An automorphic approach to verification pattern generation for SoC design verification using port-order fault model},
author = {Chun-Yao Wang and Shing-Wu Tung and Jing-Yang Jou},
year = {2002},
doi = {10.1109/TCAD.2002.802266},
url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2002.802266},
tags = {design, systematic-approach},
researchr = {https://researchr.org/publication/WangTJ02a},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {21},
number = {10},
pages = {1225-1232},
}