The following publications are possibly variants of this publication:
- Verification Pattern Generation for Core-Based Design Using Port Order Fault ModelShing-Wu Tung, Jing-Yang Jou. ats 1998: 402-407 [doi]
- An AVPG for SOC design verification with port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. iscas 2001: 259-262 [doi]
- An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault ModelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. ats 2001: 431-436 [doi]
- On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. hldvt 2001: 145-150 [doi]
- Automatic interconnection rectification for SoC design verification based on the port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 22(1):104-114, 2003. [doi]