The following publications are possibly variants of this publication:
- Yield-Driven, False-Path-Aware Clock Skew SchedulingJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. dt, 22(3):214-222, 2005. [doi]
- False Path and Clock Scheduling Based Yield-Aware Gate SizingJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. vlsid 2005: 423-426 [doi]
- Bound-based identification of timing-violating paths under variabilityLin Xie, Azadeh Davoodi. aspdac 2009: 278-283 [doi]
- Representative path selection for post-silicon timing prediction under variabilityLin Xie, Azadeh Davoodi. dac 2010: 386-391 [doi]