Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test - researchr publication related

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Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty. Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China. pages 301-306, IEEE Computer Society, 2010. [doi]

The following publications are possibly variants of this publication:

Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current LimitsWei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty. jolpe, 8(2):235-247, 2012. [doi]

Power-safe application of tdf patterns to flip-chip designs during wafer testWei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty. todaes, 18(3):43, 2013. [doi]

Power-safe test application using an effective gating approach considering current limitsWei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty. vts 2011: 160-165 [doi]

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault PatternsHassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen. jolpe, 8(2):248-258, 2012. [doi]

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC DesignNisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram. dac 2007: 533-538 [doi]

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