Abstract is missing.
- Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power ReductionSungyoul Seo, Yong Lee 0002, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang. 1-6 [doi]
- A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed TestZhou Jiang, Dong Xiang, Kele Shen. 7-12 [doi]
- A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF TransitionsMasayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa. 13-18 [doi]
- TestExpress - New Time-Effective Scan-Based Deterministic Test ParadigmGrzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang. 19-24 [doi]
- A New Scan Flip Flop Design to Eliminate Performance Penalty of ScanSatyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Matrosova, Virendra Singh. 25-30 [doi]
- Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant IdentificationMasahiro Fujita. 31-36 [doi]
- A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller AugmentationTetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara. 37-42 [doi]
- SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern GeneratorChun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang. 43-48 [doi]
- Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded MemoriesShyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume. 49-54 [doi]
- A Lightweight Timing Channel Protection for Shared Memory ControllersGuopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li. 55-60 [doi]
- On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMsJosef Kinseher, Leonardo Bonet Zordan, Ilia Polian. 61-66 [doi]
- Testing Inter-Word Coupling Faults of Wide I/O DRAMsChe-Wei Chou, Yong-Xiao Chen, Jin-Fu Li. 67-72 [doi]
- Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power ConstraintsRajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay. 73-78 [doi]
- At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore LogicKonstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen. 79-84 [doi]
- TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCsJun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li. 85-90 [doi]
- Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR KeyHejia Liu, Vishwani D. Agrawal. 91-96 [doi]
- On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open FaultsXijiang Lin, Wu-Tung Cheng, Janusz Rajski. 97-102 [doi]
- Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock StretchK. Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, J. Qian. 103-108 [doi]
- Optimized Selection of Frequencies for Faster-Than-at-Speed TestMatthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich. 109-114 [doi]
- A Methodology for Identifying High Timing Variability Paths in Complex DesignsVirendra Singh, Adit D. Singh, Kewal K. Saluja. 115-120 [doi]
- Scan-Puf: Puf Elements Selection Methods for Viable IC IdentificationDooyoung Kim, Muhammad Adil Ansari, Jihun Jung, Sungju Park. 121-126 [doi]
- Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware SecuritySabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee. 127-132 [doi]
- A Soft Error Resilient Low Leakage SRAM Cell DesignAdithyalal P. M, Shankar Balachandran, Virendra Singh. 133-138 [doi]
- Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent PathYuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 139-144 [doi]
- Diagnostic Tests and Diagnosis for Delay Faults Using Path SegmentationTino Flenker, André Sülflow, Görschwin Fey. 145-150 [doi]
- An Integrated Approach for Improving Compression and Diagnostic Properties of Test SetsSrinivasa Shashank Nuthakki, Santanu Chattopadhyay. 151-156 [doi]
- Intermittent and Transient Fault Diagnosis on Sparse Code SignaturesMichael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña, Cecilia Metra, Hans-Joachim Wunderlich. 157-162 [doi]
- SHAKTI-F: A Fault Tolerant Microprocessor ArchitectureSukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti. 163-168 [doi]
- FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated CodeSwagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Kumar Pal, Subhasish Chattopadhyay. 169-174 [doi]
- Improved Methods for Accurate Safety Analysis of Real-Life SystemsV. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur. 175-180 [doi]
- Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET CircuitsKuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li. 181-186 [doi]
- A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM ArraysAshwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury. 187-192 [doi]
- A Technique for Analyzing On-Chip Power Supply ImpedanceMasahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada. 193-198 [doi]
- In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT MechanismsPayman Behnam, Bijan Alizadeh. 199-204 [doi]
- A New Approach for Minimal Environment Construction for Modular Property VerificationSaikat Dutta, Soumi Chattopadhyay, Ansuman Banerjee, Pallab Dasgupta. 205-210 [doi]
- On the testability of IEEE 1687 networksRiccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson. 211-216 [doi]
- Design-for-testability in reversible logic circuits based on bit-swappingJoyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya. 217-222 [doi]