Abstract is missing.
- An RT-level fault model with high gate level correlationFulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero. 3-8 [doi]
- A novel methodology for hierarchical test generation using functional constraint compositionVivekananda M. Vedula, Jacob A. Abraham. 9-14 [doi]
- Use of constraint solving in order to generate test vectors for behavioral validationChristophe Paoli, Marie-Laure Nivet, Jean François Santucci. 15-20 [doi]
- Behavioral-level test vector generation for system-on-chip designsMarcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno. 21-26 [doi]
- An approach to functional testing of VLIW architecturesM. Beardo, Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto. 29-33 [doi]
- A new method for on-line state machine observation for embedded microprocessorsMatthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus. 34-39 [doi]
- Verification of in-order execution in pipelined processorsHiroyuki Tomiyama, Taisei Yoshino, Nikil Dutt. 40-44 [doi]
- Silicon debug of a co-processor array for video applicationsBart Vermeulen, Gert-Jan van Rootselaar. 47-52 [doi]
- Interface based hardware/software validation of a system-on-chipDebashis Panigrahi, Clark N. Taylor, Sujit Dey. 53-58 [doi]
- Hardware/software co-debugging for reconfigurable computingKaren A. Tomko, Anurag Tiwari. 59-63 [doi]
- Functional verification of an embedded network component by co-simulation with a real networkRobert Pasko, Radim Cmar, Patrick Schaumont, Serge Vernalde. 64-67 [doi]
- Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)M. S. Jahanpour, Eduard Cerny. 71-76 [doi]
- Simulation strategy after model checking: experience in industrial SOC designHoon Choi, Byeong-Whee Yun, Yun-Tae Lee. 77-79 [doi]
- An approach to high-level synthesis system validation using formally verified transformationsRajesh Radhakrishnan, Elena Teica, Ranga Vemuri. 80-85 [doi]
- On statistical behavior of branch coverage in testing behavioral VHDL modelsAmjad Hajjar, Tom Chen, Anneliese von Mayrhauser. 89-94 [doi]
- Variable size analysis and validation of computation qualityHajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao. 95-100 [doi]
- Code simulation concept for S/390 processors using an emulation systemStefan Koerner. 101-102 [doi]
- Formal operator testability methods for behavioral-level DFT using value rangesSandhya Seshadri, Michael S. Hsiao. 105-111 [doi]
- System level testability analysis using Petri netsTianjing Jiang, Robert H. Klenke, James H. Aylor, Gang Han. 112-117 [doi]
- High level fault simulation: experiments and results on ITC'99 benchmarksDominique Federici, Paul Bisgambiglia, Jean François Santucci. 118-123 [doi]
- On choosing test criteria for behavioral level hardware design verificationAnneliese von Mayrhauser, Tom Chen, Jan Kok, Chuck Anderson, Anita Read, Amjad Hajjar. 124-130 [doi]
- Abstraction techniques for verification of multiple tightly coupled counters, registers and comparatorsYee-Wing Hsieh, Steven P. Levitan. 133-138 [doi]
- Refining abstract equivalence analysis for embedded system designHarry Hsieh, Felice Balarin. 139-146 [doi]
- Toward automated abstraction for protocols on branching networksMichael D. Jones, Ganesh Gopalakrishnan. 147-152 [doi]
- Data flow based cache prediction using local simulationFabian Wolf, Rolf Ernst. 155-160 [doi]
- Checking temporal properties under simulation of executable system descriptionsJürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel. 161-166 [doi]
- Compilation-based software performance estimation for system level designMihai T. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, Luciano Lavagno, Marcello Lajolo. 167-172 [doi]
- Transformation of algorithmic simulation vector sets considering mapping problems of I/O operationsCordula Hansen, Wolfgang Rosenstiel. 173-178 [doi]