Abstract is missing.
- Message from the General Chair ICCD 2020Maciej Ciesielski. 1 [doi]
- Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum SystemsDaniel Volya, Prabhat Mishra 0001. 1-4 [doi]
- Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image ProcessingHimanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus. 5-8 [doi]
- Special Session: Quantum Error Correction in Near Term SystemsRitajit Majumdar, Susmita Sur-Kolay. 9-12 [doi]
- Special Session: Noise Characterization and Error Mitigation in Near-Term Quantum ComputersChristopher J. Wood. 13-16 [doi]
- Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT SystemsKrithika Dhananjay, Emre Salman. 17-20 [doi]
- Special Session: Exploring the Ultimate Limits of Adiabatic CircuitsMichael P. Frank, Robert W. Brocato, Thomas M. Conte, Alexander H. Hsia, Anirudh Jain, Nancy A. Missert, Karpur Shukla, Brian D. Tierney. 21-24 [doi]
- Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJHimanshu Thapliyal, S. Dinesh Kumar. 25-28 [doi]
- Special Session: An Adiabatic Logic Based Silicon Physical Unclonable FunctionKohei Ogura, Yasuhiro Takahashi. 29-32 [doi]
- Special Session: Potentially Leaky Controller: Examining Cache Side-Channel Attacks in Programmable Logic ControllersDimitrios Tychalas, Michail Maniatakos. 33-36 [doi]
- Special Session: Physics- Informed Neural Networks for Securing Water Distribution SystemsSolon Falas, Charalambos Konstantinou, Maria K. Michael. 37-40 [doi]
- Special Issue: Resilient Distributed Estimator with Information Consensus for CPS SecurityFeng Yu, Yaodan Hu, Teng Zhang 0002, Yier Jin. 41-44 [doi]
- Special Session: Noninvasive Sensor-Spoofing Attacks on Embedded and Cyber-Physical SystemsAnomadarshi Barua, Mohammad Abdullah Al Faruque. 45-48 [doi]
- Special Session: Harness the Power of DERs for Secure Communications in Electric Energy SystemsIoannis Zografopoulos, Juan Ospina, Charalambos Konstantinou. 49-52 [doi]
- Special Session: XTA: Open Source eXtensible, Scalable and Adaptable Tensor Architecture for AI AccelerationRavikumar V. Chakaravarthy, Hua Jiang. 53-56 [doi]
- Reconfigurable Dataflow Optimization for Spatiotemporal Spiking Neural Computation on Systolic Array AcceleratorsJeong Jun Lee, Peng Li. 57-64 [doi]
- DualFS: A Coordinative Flash File System with Flash Block Dual-mode SwitchingBing Wu, Mengye Peng, Dan Feng 0001, Wei Tong. 65-72 [doi]
- Quantum-Proof Lightweight McEliece Cryptosystem Co-processor DesignRashmi S. Agrawal, Lake Bu, Michel A. Kinsy. 73-79 [doi]
- Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet IntegrationJinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, Sung Kyu Lim. 80-87 [doi]
- Driving Scenario Perception-Aware Computing System Design in Autonomous VehiclesHengyu Zhao, Yubo Zhang, Pingfan Meng, Hui Shi, Li Erran Li, Tiancheng Lou, Jishen Zhao. 88-95 [doi]
- MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ ComputingAnuradha Chathuranga Ranasinghe, Sabih H. Gerez. 96-104 [doi]
- FAGR: An Efficient File-aware Graph Recovery Scheme for Erasure Coded Cloud Storage SystemsHeming Zeng, Chi Zhang, Chentao Wu, Gen Yang, Jie Li 0002, Guangtao Xue, Minyi Guo. 105-112 [doi]
- An Efficient Hardware Architecture for Finding Frequent Items in Data StreamsAli Ebrahim, Jalal Khlaifat. 113-119 [doi]
- NATSA: A Near-Data Processing Accelerator for Time Series AnalysisIvan Fernandez, Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata, Christina Giannoula, Mohammed Alser, Juan Gómez-Luna, Onur Mutlu. 120-129 [doi]
- MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic ArchitectureBahar Asgari, Ramyad Hadidi, Hyesoon Kim. 130-137 [doi]
- QuPAA: Exploiting Parallel and Adaptive Architecture to Scale up Quantum ComputingYingxun Fu, Yao Sun, Tao Li. 138-145 [doi]
- PBCCF: Accelerated Deduplication by Prefetching Backup Content Correlated FingerprintsYaobin Qin, Xianbo Zhang, David J. Lilja. 146-154 [doi]
- EaD: a Collision-free and High Performance Deduplication Scheme for Flash Storage SystemsSuzhen Wu, Jindong Zhou, Weidong Zhu, Hong Jiang 0001, Zhijie Huang, Zhirong Shen, Bo Mao. 155-162 [doi]
- COSMA: An Efficient Concurrency-Oriented Space Management Scheme for In-memory File SystemsChunhua Xiao, Zipei Feng, Ting Wu, Lin Zhang, Xiaoxiang Fu, Weichen Liu. 163-166 [doi]
- AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDsTianqi Zhan, Xianpeng Wang, Dan Feng 0001, Wei Tong. 167-174 [doi]
- An Empirical Study of Hybrid SSD with Optane and QLC FlashHui Chen, Yina Lv, Changlong Li, Shouzhen Gu, Liang Shi. 175-178 [doi]
- ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering TechniqueMehran Goli, Alireza Mahzoon, Rolf Drechsler. 179-186 [doi]
- WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address DecodersLeonid Yavits, Lois Orosa 0001, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu. 187-196 [doi]
- DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error PreventionXiaoming Du, Cong Li. 197-204 [doi]
- Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip ArchitectureRomain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet. 205-212 [doi]
- ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural NetworksHaoqiang Guo, Lu Peng, Jian Zhang 0004, Qing Chen, Travis LeCompte. 213-221 [doi]
- APAC: An Accurate and Adaptive Prefetch Framework with Concurrent Memory Access AnalysisXiaoyang Lu, Rujia Wang, Xian-He Sun. 222-229 [doi]
- Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router BuffersAbhijit Das 0002, Abhishek Kumar, John Jose. 230-238 [doi]
- Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core ProcessorsJoe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam. 239-246 [doi]
- A Study of Runtime Adaptive Prefetching for STTRAM L1 CachesKyle Kuan, Tosiron Adegbija. 247-254 [doi]
- Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address TranslationZhulin Ma, Yujuan Tan, Hong Jiang 0001, Zhichao Yan, Duo Liu, Xianzhang Chen, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chengliang Wang. 255-262 [doi]
- Runtime Deep Model Multiplexing for Reduced Latency and Energy Consumption InferenceAmir Erfan Eshratifar, Massoud Pedram. 263-270 [doi]
- Near-Sensor Inference Architecture with Region Aware ProcessingMd Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda. 271-278 [doi]
- A Distributed In-Situ CNN Inference System for IoT ApplicationsJiangsu Du, Minghua Shen, Yunfei Du. 279-287 [doi]
- EdgeNAS: Discovering Efficient Neural Architectures for Edge SystemsXiangzhong Luo, Di Liu, Hao Kong, Weichen Liu. 288-295 [doi]
- EM-GAN: Data-Driven Fast Stress Analysis for Multi-Segment InterconnectsWentian Jin, Sheriff Sadiqbatcha, Zeyu Sun, Han Zhou, Sheldon X.-D. Tan. 296-303 [doi]
- Maximum Clique Based Method for Optimal Solution of Pattern ClassificationXu He, Yipei Wang, Zhiyong Fu, Yao Wang 0002, Yang Guo. 304-311 [doi]
- Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at RuntimeVladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler. 312-315 [doi]
- Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level SynthesisMarcos T. Leipnitz, Gabriel L. Nazar. 316-323 [doi]
- Learn to Floorplan through Acquisition of Effective Local Search HeuristicsZhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu 0001, Martin D. F. Wong. 324-331 [doi]
- 4-output Programmable Spin Wave Logic GateAbdulqader Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana. 332-335 [doi]
- Bespoke Behavioral ProcessorsRohit Sreekumar, Prattay Chowdhury, Benjamin Carrión Schäfer. 336-339 [doi]
- Hardware-based Fast Real-time Image Classification with Stochastic ComputingPonnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes. 340-347 [doi]
- Scaled Population Subtraction for Approximate ComputingKunal Bharathi, Jiang Hu, Sunil P. Khatri. 348-355 [doi]
- Programmable Dictionary Code Compression for Instruction Stream Energy EfficiencyJoonas Multanen, Kari Hepola, Pekka Jääskeläinen. 356-363 [doi]
- An Open-Source Scalable Thermal and Power Controller for HPC ProcessorsGiovanni Bambini, Robert Balas, Christian Conficoni, Andrea Tilli, Luca Benini, Simone Benatti, Andrea Bartolini. 364-367 [doi]
- IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-MemorySandeep Krishna Thirumala, Arnab Raha, Vijay Raghunathan, Sumeet Kumar Gupta. 368-376 [doi]
- Improving the Efficiency of Power Management via Dynamic Interrupt ManagementKi-Dong Kang, Hyungwon Park, Gyeongseo Park, Daehoon Kim. 377-380 [doi]
- OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAsCheng Tan, Chenhao Xie 0001, Ang Li, Kevin J. Barker, Antonino Tumeo. 381-388 [doi]
- PerfDBT: Efficient Performance Regression Testing of Dynamic Binary TranslationJin Wu, Jian Dong, Ruili Fang, Wenwen Wang, Decheng Zuo. 389-392 [doi]
- Transforming Natural Language Specifications to Logical Forms for Hardware VerificationRahul Krishnamurthy, Michael S. Hsiao. 393-396 [doi]
- Accelerated Verification of Parametric Protocols with Decision TreesYongjian Li, Taifeng Cao, David N. Jansen, Jun Pang 0001, Xiaotao Wei. 397-404 [doi]
- H2ORAM: Low Response Latency Optimized ORAM for Hybrid Memory SystemsWenpeng He, Fang Wang 0001, Dan Feng 0001. 405-408 [doi]
- Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack MemoryRui Xu, Edwin H.-M. Sha, Qingfeng Zhuge, Shouzhen Gu, Liang Shi. 409-416 [doi]
- Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) IntegrationChao-Hsuan Huang, Ishan G. Thakkar. 417-420 [doi]
- ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid CachesBeomjun Kim, Prashant J. Nair, Seokin Hong. 421-424 [doi]
- A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space ApplicationsAnthony Agnesina, Da Eun Shim, James Yamaguchi, Christian Krutzik, John Carson, Dan Nakamura, Sung Kyu Lim. 425-432 [doi]
- A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard CellsAnkit Wagle, Sunil Khatri, Sarma B. K. Vrudhula. 433-440 [doi]
- On the Effects of Permanent Faults in QDI Circuits - A Quantitative PerspectiveRaghda El Shehaby, Andreas Steininger. 441-444 [doi]
- A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point MultiplierS. Ross Thompson, James E. Stine. 445-452 [doi]
- An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2VFarid Uddin Ahmed, Zarin Tasnim Sandhie, Masud H. Chowdhury. 453-456 [doi]
- Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHzWei Chu, Wei-Hao Chen, Shi-Yu Huang. 457-460 [doi]
- High Throughput CNN Inference and Training with In-Cache ComputationXiaowei Wang, Li Zhao, Pengcheng Li. 461-464 [doi]
- Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture SearchHongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk. 465-468 [doi]
- Achieving Full Parallelism in LSTM via a Unified Accelerator DesignXinyi Zhang, Weiwen Jiang, Jingtong Hu. 469-477 [doi]
- A Hybrid Computing Architecture for Fault-tolerant Deep Learning AcceleratorsDawen Xu 0002, Cheng Chu, Qianlong Wang, Cheng Liu, Ying Wang 0001, Lei Zhang, Huaguo Liang, Kwang-Ting Cheng. 478-485 [doi]
- Dynamic Heterogeneous Voltage Regulation for Systolic Array-Based DNN AcceleratorsJianhao Chen, Joseph Riad, Edgar Sánchez-Sinencio, Peng Li 0001. 486-493 [doi]
- CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural NetworksRui Xu, Sheng Ma, Yaohua Wang, Yang Guo 0003. 494-497 [doi]
- Thermal Aware Lifetime Reliability Optimization for Automotive Distributed Computing ApplicationsAjinkya S. Bankar, Shi Sha, Vivek Chaturvedi, Gang Quan. 498-505 [doi]
- On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and PortabilityMd Toufiq Hasan Anik, Mohammad Ebrahimabadi, Hamed Pirsiavash, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi. 506-509 [doi]
- Re-Thinking Mixed-Criticality Architecture for Automotive IndustryZhe Jiang 0004, Shuai Zhao 0004, Pan Dong, Dawei Yang, Ran Wei, Nan Guan, Neil C. Audsley. 510-517 [doi]
- Design- Time Optimization of Reconfigurable PV Architectures for Irregular SurfacesSangyoung Park, Swaminathan Narayanaswamy, Samarjit Chakraborty. 518-524 [doi]
- pacSCA: A Profiling-Assisted Correlation-based Side-Channel Attack on GPUsXin Wang, Wei Zhang. 525-528 [doi]
- BranchSpec: Information Leakage Attacks Exploiting Speculative Branch Instruction ExecutionsMd Hafizul Islam Chowdhuryy, Hang Liu, Fan Yao. 529-536 [doi]
- ND-HMDs: Non-Differentiable Hardware Malware Detectors against Evasive Transient Execution AttacksMd. Shohidul Islam, Abraham Peedikayil Kuruvila, Kanad Basu, Khaled N. Khasawneh. 537-544 [doi]
- Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAsYukui Luo, Cheng Gongye, Shaolei Ren, Yunsi Fei, Xiaolin Xu. 545-552 [doi]
- Side-Channel Leakage Detection Based on Constant Parameter Channel ModelWei Yang, Hailong Zhang, Yansong Gao, Anmin Fu, Songjie Wei. 553-560 [doi]
- Improving the Performance of NVM Crash Consistency under MulticoreZhiyuan Lu, Jianhui Yue, Yifu Deng, Yifeng Zhu. 561-564 [doi]
- More Space may be Cheaper: Multi-Dimensional Resource Allocation for NVM-based Cloud CacheNing Bao, Yunpeng Chai, Yuxuan Zhang, Chuanwen Wang, Dafang Zhang. 565-572 [doi]
- Isle-Tree: A B+-Tree with Intra-Cache Line Sorted Leaves for Non-volatile MemoryChundong Wang 0001, Sudipta Chattopadhyay 0001. 573-580 [doi]
- Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile MemoryWei Li, Libing Wu, Mengting Yuan, Chun Jason Xue, Jingling Xue, Qingan Li. 581-588 [doi]
- Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus InterfaceJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 589-596 [doi]
- Z2-ZNCC: ZigZag Scanning based Zero-means Normalized Cross Correlation for Fast and Accurate Stereo Matching on Embedded GPUQiong Chang, Aolong Zha, Weimin Wang, Xin Liu, Masaki Onishi, Tsutomu Maruyama. 597-600 [doi]
- Exploring Better Speculation and Data Locality in Sparse Matrix-Vector Multiplication on Intel XeonHaoran Zhao, Tian Xia, Chenyang Li, Wenzhe Zhao, Nanning Zheng 0001, Pengju Ren. 601-609 [doi]
- pRnR: A Parallel Record-Replay Framework for Virtual MachinesWei Wang, Lei Cui 0003, Zhiyu Hao, Haiqiang Fei, Chonghua Wang, Yaqiong Peng. 610-618 [doi]
- ANSim: A Fast and Versatile Asynchronous Network-On-Chip SimulatorTom Glint, Jitesh Sah, Manu Awasthi, Joycee Mekie. 619-622 [doi]
- ALT: Optimizing Tensor Compilation in Deep Learning Compilers with Active LearningXi Zeng, Tian Zhi, Zidong Du, Qi Guo 0001, Ninghui Sun, Yunji Chen. 623-630 [doi]
- Chain-Based Fixed-Priority Scheduling of Loosely-Dependent TasksHyunjong Choi, Mohsen Karimi, Hyoseung Kim. 631-639 [doi]
- Attacking Trivium at the Bitstream LevelKalle Ngo, Elena Dubrova, Michail Moraitis. 640-647 [doi]
- Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel AttacksHan Wang, Hossein Sayadi, Gaurav Kolhe, Avesta Sasan, Setareh Rafatirad, Houman Homayoun. 648-655 [doi]
- ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSSPrashanth Mohan, Wen Wang 0007, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai. 656-662 [doi]
- Hardware-Assisted Malware Detection using Explainable Machine LearningZhixin Pan, Jennifer Sheldon, Prabhat Mishra 0001. 663-666 [doi]