Abstract is missing.
- Micro-Checkpointing: Checkpointing for Multithreaded ApplicationsKeith Whisnant, Zbigniew Kalbarczyk, Ravishankar K. Iyer. 3-8 [doi]
- A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NTAlfredo Benso, Silvia Chiusano, Paolo Prinetto. 9-16 [doi]
- Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based ArchitecturesMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco. 17 [doi]
- Relation between Fault Tolerance and Reconfiguration in Cellular SystemsLukás Sekanina, Vladimír Drábek. 25-30 [doi]
- Improving On-Line BIST-Based Diagnosis for Roving STARsMiron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert. 31-39 [doi]
- Self-Testing of FPGA Delay Faults in the System EnvironmentAndrzej Krasniewski. 40 [doi]
- A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI CircuitsJ. A. Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca. 45-51 [doi]
- An Overview of the Applications of a Pulsed Laser System for SEU TestingV. Pouget, Pascal Fouillat, D. Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet. 52 [doi]
- New Techniques for Accelerating Fault Injection in VHDL DescriptionsB. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 61-66 [doi]
- Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDLFabian Vargas, Alexandre M. Amory, Raoul Velazco. 67-72 [doi]
- A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer SystemDaniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil. 73-79 [doi]
- Transient Bitflip Injection in Microprocessor Embedded ApplicationsRaoul Velazco, Sana Rezgui. 80 [doi]
- On-Line Current Testing for a Microprocessor Based Application with an Off-Chip SensorB. Alorda, Ivan de Paúl, Jaume Segura, T. Miller. 87-91 [doi]
- I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog TestMartin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková. 92-93 [doi]
- A Compact Built-In Current Sensor for IDDQ TestingY. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos. 95-99 [doi]
- An Improved CMOS BICS for On-Line TestingY. Maidon, Yann Deval, Jean-Baptiste Begueret. 100 [doi]
- Concurrent Scan Monitoring and Multi-Pattern SearchJose Miguel Vieira dos Santos. 107-111 [doi]
- Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital SystemsAhmad Abdelhay, Emmanuel Simeu. 112 [doi]
- Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging FaultsPatrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 121-126 [doi]
- On Using Deterministic Test Sets in BISTOndrej Novák, Jiri Nosek. 127-132 [doi]
- Power Reduction in Test-Per-Scan BISTXiaodong Zhang, Kaushik Roy. 133 [doi]
- New Self-Checking Circuits by Use of Berger-CodesA. Morozov, V. V. Saposhnikov, Vl. V. Saposhnikov, Michael Gössel. 141-146 [doi]
- A New Method for Concurrent Checking by Use of a 1-out-of-4 CodeMichael Gössel, Alexej Dmitriev, Vl. V. Saposhnikov, V. V. Saposhnikov. 147-152 [doi]
- Self-Checking FSM Design with Observing only FSM OutputsA. Matrosova, Sergey Ostanin. 153-154 [doi]
- Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog ICPaolo Migliavacca. 155 [doi]
- Theoretical Performance Bounds of a Probability of Bit Error Estimator Used in Digital Links Employing Binary Block CodesK. D. R. Jagath-Kumara. 165-168 [doi]
- A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS CodeT. Vallino, Abbas Dandache, J. P. Delahaye, Fabrice Monteiro, Bernard Lepley. 169-170 [doi]
- Low Cost Concurrent Error Detection Based on Modulo Weight-Based CodesDebaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel. 171 [doi]
- A Very Flexible DSP-Based Controller for On-Line Test and Control of Industrial ProcessesM. E. Nillesen, A. Del Pizzo, M. Pasquariello, R. Rizzo. 179-184 [doi]
- On Realization of Fault-Tolerant Fuzzy ControllersNaotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui. 185-190 [doi]
- ISIS: A Fail-Safe Interface Realized in Smart Power TechnologyMichael Nicolaidis, N. Zaidan, Th. Calin, D. Bied-Charreton. 191 [doi]
- High-Level Synthesis Methodology for On-Line Testability OptimizationMohammad A. Naal, Emmanuel Simeu. 201-206 [doi]
- Improving Fault Coverage in System TestsJanusz Sosnowski. 207-213 [doi]
- A Family of Self-Repair SRAM CoresAlfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni. 214-218 [doi]