Abstract is missing.
- A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICsHuaguo Liang, Danqing Li, Zhao Yang, Tianming Ni, Zhengfeng Huang, Cuiyun Jiang. 1-5 [doi]
- Identification of Counter Registers through Full Scan ChainQidong Wang, Aijiao Cui, Gang Qu 0001. 1-5 [doi]
- *Arjun Chaudhuri, Krishnendu Chakrabarty. 1-6 [doi]
- Integrated Scratch Marker for Wafer Defect DiagnosisKatherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng. 1-4 [doi]
- TAIWAN Online: Test AI with AN Codes Online for Automotive ChipsCheng-Di Tsai, Hsiao-Wen Fu, Ting-Yu Chen, Tsung-Chu Huang. 1-6 [doi]
- Developing Formal Models for Measuring Fault Effects Using Functional EDA ToolsWei Hu 0008, Jing Tan, Lingjuan Wu, Yu Tai, Liang Hong. 1-6 [doi]
- High-speed measurement of Piezoelectric MEMS equivalent circuit parameters by Swept-sine and PRBS signalsMitsuo Matsumoto, Masayuki Kawabata, Yukio Kawanabe. 1-6 [doi]
- Use Machine Learning Based Smart Sampling to Improve System Level Testing EfficiencyChenwei Liu, Jie Ou. 1-6 [doi]
- Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust ComputingAibin Yan, Zijie Zhai, Lele Wang, JiXiang Zhang, Ningning Cui, Tianming Ni, Xiaoqing Wen. 1-5 [doi]
- Automotive Test and ReliabilityYu Huang 0005, David Francis, Yervant Zorian, Nilanjan Mukherjee 0001. 1 [doi]
- An optimized DFT technology based on machine learningHan Yang, Zeyu Zhao, Zhikuang Cai. 1-4 [doi]
- The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUFXiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui. 1-6 [doi]
- A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock SignalChen-Lin Tsai, Wei-Hao Chen, Shi-Yu Huang. 1-6 [doi]
- Fault Modeling and Testing of Spiking Neural Network ChipsYi-Zhan Hsieh, Hsiao-Yin Tseng, I-Wei Chiu, James Chien-Mo Li. 1-6 [doi]
- Scalable Parallel Static LearningXiaoze Lin, Liyang Lai, Huawei Li. 1-6 [doi]
- Automatic Test Program Generation for Transition Delay Faults in Pipelined ProcessorsKai-Hsun Chen, Bo-Yi Yang, Jia-Ruei Liang, Hung-Lin Chen, Jiun-Lang Huang. 1-6 [doi]
- The Advancement of 1149.10Yu Huang, Haitao Fu, Bin Deng, Edward Seng, Marc Hutner, Jean-Francois Cote, Geir Eide. 1 [doi]
- AMSER-FF: Area-Minimized Soft-Error-Recoverable Flip-Flop for Radiation HardeningJohn Z.-L. Tang, Dave Y.-W. Lin, Ralf E.-H. Yee, Charles H.-P. Wen. 1-6 [doi]
- A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch DesignShuo Cai, Caicai Xie, Yan Wen, Weizheng Wang. 1-5 [doi]
- Diagnosis and Yield LearningYu Huang 0005, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige. 1 [doi]
- Kelvin Bridge Structure Based TSV Test for Weak FaultsChang Hao, Zhengfeng Huang, Tianming Ni. 1-6 [doi]
- Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal ProbabilityZhen Wang, Guofa Zhang, Jing Ye, Jianhui Jiang. 1-6 [doi]
- An SRAM Test Quality Improvement Method For Automotive chipsTuanhui Xu, Junlin Huang, Mingen Bu, Zhe Jiang. 1-4 [doi]
- Rigorous Test Flow for PLL to Identify Weak DevicesYi-Hsuan Lee, Shi-Yu Huang. 1-6 [doi]