Table of Contents

• Validation and Verification of Complex Digital Systems: A Practical PerspectiveLi-C. Wang, Magdy S. Abadir. 1
• An Overview Covering the Different Solutions: from radiation testing to Software Fault InjectionMatteo Sonza Reorda. 2
• A New On-Line Robust Approach to Design Noise-Immune Speech Recognition SystemsFabian Vargas 0001, Rubem D. R. Fagundes, Daniel Barros Jr.. 4-10
• Fault-Tolerant Predictive Feedback ControlLeonardo L. Giovanini. 11-15
• Non-stationary Communication Dalays in Failure DetectorsRaul Ceretta Nunes, Ingrid Jansch-Pôrto. 16-21
• A New Approach to Software-Implemented Fault ToleranceMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 22-25
• A Software Technique for Fault-Tolerant Adaptive Circuits in Spatial ApplicationsJoão-Batista Destro-Filho, M. V. Ribeiro. 26-31
• DMutation Analysis and Constraint-Based Criteria: Results from na Empirical Evaluation in the Context of Testing SoftwareInali Wisniewski Soares, Silvia Regina Vergilio. 33-38
• A Flexible Approach for Defining Distributed Dependable Tests in SNMP-based Network Management SystemsLuis Carlos Erpen De Bona, Elias Procópio Duarte Jr.. 39-44
• Software Testing in Client-Server Environments: a Strategy and its ApplicationLisiane Maes Volpi, Silvia Regina Vergilio. 45-50
• On High-Quality, Low Energy BIST Preparation at RT-LevelMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Luz Balado, Joan Figueras. 52-57
• Built-in Self Code for Microcontroller UnitsAlexandre S. Santiago, Arthur H. C. Oliveira, Rubens Takiguti. 58-60
• A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST ApplicationsWang Jiang Chau, Paulo Sérgio Cardoso, Marius Strum, Ricardo Pires. 61-63
• BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional UnitsWang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires. 64-69
• Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-based FPGA Structural Concurrent Test MethodologyManuel G. Gericota, Gustavo R. Alves. 70-75
• A New FPGA for DSP Applications Integrating BIST CapabilitiesAlex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell. 76-81
• Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any OrderJosé Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski, Antonio Carneiro de Mesquita Filho. 83-85
• State Model Approach for Analog Fault ModelingJosé Vicente Calvano, Antonio Carneiro de Mesquita Filho, Marcelo Lubaszewski, Vladimir Castro Alves. 86-88
• Low-cost on-chip measurements for Oscillation-Based-Test in Analog Integrated CircuitsDiego Vázquez, Gloria Huertas, Adoración Rueda, Gildas Léger, José L. Huertas. 89-93
• Oscillation Test Strategy: a Case StudyEduardo Romero 0002, Gabriela Peretti, Carlos A. Marqués. 94-98
• Testing Resonant Micro-Electro-Mechanical Sensors using the Oscillation-based Test MethodologyVincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet. 99-104
• SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor SystemPablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Raul Velazco, Ricardo T. Ferreyra. 106-108
• Dynamic Fault Injection in Integrated Circuits with a Pulsed LaserDean Lewis, Pascal Fouillat, Vincent Pouget. 109-113
• SEU fault injection in simulation environments: example of VHDL configuration on FPGA deviceIvan de Paúl, Miquel Roca, Oscar Calvo, Raul Velazco. 114-119
• Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controllerFernanda Lima 0001, Luigi Carro, Raul Velazco, Ricardo Reis 0001. 120-125
• Simulating Single Event Transients in VDSM ICs for Ground Level RadiationDan Alexandrescu, Lorena Anghel, Michael Nicolaidis. 126-129
• Laser Utilization for Various Testing PurposesPascal Fouillat. 130
• Efficient and Exact Diagnosis of Multiple Stuck-At FaultsJiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir. 132-136
• Testability Calculation for Digital Circuits with Decision DiagramsRaimund Ubar. 137-143
• A Comparison Between Testability Measures Applied to Complex GatesJosé Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis 0001. 144-149
• Seamless Testing of Embedded Control SystemsEric Sax, J. Willibald, Klaus D. Müller-Glaser. 151-153
• Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GAZahra Sadat Ebadi, André Ivanov. 154-159
• Generic and Detailed Search for TAM Definition in Core-Based SystemsÉrika F. Cota, Luigi Carro, Alex Orailoglu, Marcelo Lubaszewski. 160-164
• Complex Adaptive Signal Processing for Analog TestingAdão Antonio de Souza Junior, Marcelo Negreiros, Luigi Carro, Altamiro A. Suzim. 166-173
• Estimating Static Parameters of A-to-D Converters from Spectral AnalysisFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski. 174-179
• Hard-to-Detect Faults by Dinamic Current Sensor in Analogue CircuitsYolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho. 180-185
• IDDQ Testing for Deep Submicron ICs: Challenges and SolutionsZhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001. 186-192
• Specific Tests of Thin Film Devices for Large Area ElectronicsOlivier Bonnaud, Taieb Mohammed-Brahim. 194-198
• Multi-Level Testing Strategy for Radiation Hardened SOI/SOS ICsKonstantin O. Petrosjanc, Igor A. Kharitonov, Alexej S. Adonin. 199-204
• Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory ElementsAntonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo. 205-211
• Very Fast Reliability Test at Wafer Level Applied to a BCD TechnologyOlivier Bonnaud. 212