Table of Contents

• Architecting energy efficient crossbar-based memristive random-access memoriesMiguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng. 1-6 [doi]
• An architecture-level cache simulation framework supporting advanced PMA STT-MRAMBi-Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao. 7-12 [doi]
• MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memoriesAli Alsuwaiyan, Kartik Mohanram. 13-18 [doi]
• Lossy frequency selective surfaces for gas sensing using ZnO filmsColin Pardue, Madhavan Swaminathan, John Bosco Balaguru. 19-20 [doi]
• Fundamental limits of energy dissipation in spintronic interconnects using optical spin pumpingS. Rakheja. 21-22 [doi]
• Wave-based device scaling concept for brain-like energy efficiency and integrationYasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Gouhei Tanaka. 23-24 [doi]
• Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoningSantosh Khasanvis, Mingyu Li, Mostafizur Rahman, Mohammad Salehi Fashami, Ayan Kumar Biswas, Jayasimha Atulasimha, Supriyo Bandyopadhyay, Csaba Andras Moritz. 25-26 [doi]
• Robust magnetic full-adder with voltage sensing 2T/2MTJ cellErya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao. 27-32 [doi]
• Hierarchical composition of memristive networks for real-time computingJens Bürger, Alireza Goudarzi, Darko Stefanovic, Christof Teuscher. 33-38 [doi]
• A sudden power-outage resilient nonvolatile microprocessor for immediate system recoveryNaoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu. 39-44 [doi]
• NEM relay design with biconditional binary decision diagramsWinston Haaswijk, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 45-50 [doi]
• NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBsAzam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal. 51-56 [doi]
• Computation-in-memory based parallel adderHoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui, Koen Bertels. 57-62 [doi]
• Hierarchical design of robust and low data dependent FinFET based SRAM arrayMohsen Imani, Shruti Patil, Tajana Simunic Rosing. 63-68 [doi]
• Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS)Erik P. DeBenedictis, Jeanine E. Cook, Mark F. Hoemmen, Tzevetan S. Metodi. 69-74 [doi]
• Ex-situ training of dense memristor crossbar for neuromorphic applicationsRaqibul Hasan, Chris Yakopcic, Tarek M. Taha. 75-81 [doi]
• Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arraysOnur Tunali, Mustafa Alton. 82-87 [doi]
• Fast march tests for defects in resistive memorySeyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis. 88-93 [doi]
• Analogue auto-associative memory using a multi-valued memristive memory cellMohammad Mahmoud A. Taha, Wim J. C. Melis. 94-99 [doi]
• Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memoriesPeyman Pouyan, Esteve Amat, Antonio Rubio. 100-105 [doi]
• Memristor panic - A survey of different device models in crossbar architecturesWalt Woods, Mohammad Mahmoud A. Taha, S. J. Dat Tran, Jens Bürger, Christof Teuscher. 106-111 [doi]
• Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nmPablo Royer, Fernando Garcia-Redondo, Marisa López-Vallejo. 112-117 [doi]
• From kekule cells to molecular switchesAaron Germuth, Alex Aravind. 118-123 [doi]
• Interconnect networks for memristor crossbarLei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels. 124-129 [doi]
• Automated synthesis of crossbars for nanoscale computing using formal methodsAlvaro Velasquez, Sumit Kumar Jha. 130-136 [doi]
• Defect consideratons for robust sparse coding using memristor arraysPatrick Sheridan, Wei D. Lu. 137-138 [doi]
• Low area overhead in-situ training approach for memristor-based classifierElham Zamanidoost, Michael Klachko, Dmitri Strukov, Irina Kataeva. 139-142 [doi]
• Magnetoresistance implications for complementary magnetic tunnel junction logic (CMAT)Joseph S. Friedman, Damien Querlioz, Alan V. Sahakian. 143-144 [doi]
• Transmission gate-based approximate adders for inexact computingZhixi Yang, Jie Han, Fabrizio Lombardi. 145-150 [doi]
• Matrix multiplication by an inexact systolic arrayKe Chen, Fabrizio Lombardi, Jie Han. 151-156 [doi]
• Architecting 3-D integrated circuit fabric with intrinsic thermal management featuresMostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz. 157-162 [doi]
• Full-adder circuit design based on all-spin logic deviceQi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao. 163-168 [doi]
• Architecting NP-Dynamic SkybridgeJiajun Shi, Mingyu Li, Mostafizur Rahman, Santosh Khasanvis, Csaba Andras Moritz. 169-174 [doi]
• Architecting connectivity for fine-grained 3-D vertically integrated circuitsSantosh Khasanvis, Mostafizur Rahman, Mingyu Li, Jiajun Shi, Csaba Andras Moritz. 175-180 [doi]
• Supervised learning with organic memristor devices and prospects for neural crossbar arraysChristopher H. Bennett, Djaafar Chabi, Theo Cabaret, Bruno Jousselme, Vincent Derycke, Damien Querlioz, Jacques-Olivier Klein. 181-186 [doi]
• Exploiting local connectivity of CMOL architecture for highly parallel orientation selective neuromorphic chipsMelika Payvand, Luke Theogarajan. 187-192 [doi]
• On the impact of OxRAM-based synapses variability on convolutional neural networks performanceDaniele Garbin, Elisa Vianello, Olivier Bichler, M. Azzaz, Quentin Rafhay, Philippe Candelier, Christian Gamrat, Gérard Ghibaudo, Barbara De Salvo, Luca Perniola. 193-198 [doi]