Abstract is missing.
- Difficulty of predicting interconnect delay in a timing driven FPGA CAD flowValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. 3-8 [doi]
- A priori prediction of tightly clustered connections based on heuristic classification treesPranav Anbalagan, Jeffrey A. Davis. 9-15 [doi]
- A tale of two nets: studies of wirelength progression in physical designAndrew B. Kahng, Sherief Reda. 17-24 [doi]
- An overview of on-chip interconnect variationLouis Scheffer. 27-28 [doi]
- Generation of design guarantees for interconnect matchingAndrew B. Kahng, Rasit Onur Topaloglu. 29-34 [doi]
- Statistical analysis and optimization in the presence of gate and interconnect delay variationsChandu Visweswariah. 37 [doi]
- Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?Wenyi Feng, Jonathan W. Greene. 41-48 [doi]
- The routability of multiprocessor network topologies in FPGAsManuel Saldaña, Lesley Shannon, Paul Chow. 49-56 [doi]
- Congestion modeling for reconfigurable inter-processor networksWim Heirman, Joni Dambre, Jan M. Van Campenhout. 59-66 [doi]
- Modeling and analysis of the system bus latency on the SoC platformYoung-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho. 67-74 [doi]
- Energy/area/delay trade-offs in the physical design of on-chip segmented bus architectureJin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor. 75-81 [doi]
- Impact of interconnect resistance increase on system performance of low power and high performance designsMandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex. 85-90 [doi]
- Statistical crosstalk aggressor alignment aware interconnect delay calculationAndrew B. Kahng, Bao Liu, Xu Xu. 91-97 [doi]
- Constant impedance scaling paradigm for interconnect synthesisJ. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne. 99-105 [doi]
- The scaling of interconnect buffer needsPrashant Saxena. 109-112 [doi]
- Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regimeRoshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen. 113-120 [doi]