Table of Contents

• 2D Bifurcations and Chaos in Nonlinear Circuits: a Parallel Computational ApproachWieslaw Marszalek, Jan Sadecki. 1-300 [doi]
• Loss Behavioral Modeling for Ferrite InductorsGiulia Di Capua, Nicola Femia, Kateryna Stoyka. 1-9 [doi]
• Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing DetectorAndreas Herrmann, Michael Weiner, Michael Pehl, Helmut Graeb. 1-4 [doi]
• Metamodel-Based Performance Evaluation for an Electromechanical Automotive SystemChristine Forster, Jérôme Kirscher, Linus Maurer, Georg Pelz. 1-9 [doi]
• Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAsFábio Passos, Ricardo Martins 0003, Nuno C. Lourenço, Elisenda Roca, R. Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández. 1-164 [doi]
• LUT-Based Stochastic Modeling for Non-Normal Performance DistributionsMaike Taddiken, Theodor Hillebrand, Steffen Paul, Dagmar Peters-Drolshagen. 1-217 [doi]
• An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IPEzgi Kaya, Engin Afacan, Günhan Dündar. 1-9 [doi]
• Behavioral Switching Loss Modeling of Inverter ModulesKateryna Stoyka, Ricieri Akihito Pessinatti Ohashi, Nicola Femia. 1-120 [doi]
• A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz ApplicationsAntónio Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço 0003, Jorge Guilherme, Nuno Horta. 1-4 [doi]
• Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard TrackerGian-Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò. 1-20 [doi]
• PlenariesMarcel Urban, Sachin S. Sapatnekar, Richard Shi. 1-2 [doi]
• Compact Drain Current Model of Nanoscale FinFET Considering Short Channel Effect in Ballistic Transport RegimeMin Soo Bae, Chuntaek Park, Ilgu Yun. 1-112 [doi]
• Antenna Modeling Technique for Digital Communication SystemsMohammed A. Almoteriy, Mohamed I. Sobhy, John C. Batchelor. 1-48 [doi]
• Linearizing the Transconductance of an OTA Through the Optimal Sizing by Applying NSGA-IILuis Gerardo de la Fraga, Esteban Tlelo-Cuautle. 1-9 [doi]
• SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAsSarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, L. Cattaneo. 1-52 [doi]
• Modelling Switched-Capacitor DC-DC Converters with Signal Transition GraphsDanhui Li, Delong Shang, Fei Xia, Alex Yakovlev. 1-100 [doi]
• Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICsA. Toro-Frias, P. Martín-Lloret, J. Martinez, R. Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández. 1-9 [doi]
• Reliability Based Hardware Trojan Design Using Physics-Based Electromigration ModelsChase Cook, Sheriff Sadiqbatcha, Zeyu Sun, Sheldon X.-D. Tan. 5-8 [doi]
• Analysis and Modeling of a Novel SDR-Based High-Precision Positioning SystemGiovanni Piccinni, Gianfranco Avitabile, Giuseppe Coviello, Claudio Talarico. 13-16 [doi]
• Accelerating Electromigration Wear-Out Effects Based on Configurable Sink-Structured WiresSheriff Sadiqbatcha, Chase Cook, Zeyu Sun, Sheldon X.-D. Tan. 21-24 [doi]
• Variability Analysis Tool for CMOS Analog/RF Circuits: VariAnTEngin Afacan, Yigit Ender Avci, Omer Osman Demirbas. 25-28 [doi]
• Automated Massive RTN Characterization Using a Transistor Array ChipP. Saraza-Canflanca, Javier Diaz-Fortuny, A. Toro-Frias, R. Castro-López, Elisenda Roca, Javier Martín-Martínez, R. Rodrigucz, Montserrat Nafría, Francisco V. Fernández. 29-32 [doi]
• Testability Analysis Based on Complex-Field Fault ModelingGiuseppe Fontana 0001, Francesco Grasso, Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli, Alberto Reatti. 33-36 [doi]
• The Reactance Transformation for Near Sidelobes Reduction: A Comparison of Windowing TechniquesPietro Burrascano, Stefano Laureti, Marco Ricci. 37-40 [doi]
• A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability SimulationJavier Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-López, Javier Martín-Martínez, Elisenda Roca, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría. 53-56 [doi]
• Voltage Adaptation Under Temperature VariationHussam Amrouch, Behnam Khaleghi, Jörg Henkel. 57-60 [doi]
• Yield Approximation of Analog Integrated Circuits Under Time-Dependent VariabilityTheodor Hillebrand, Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen. 65-68 [doi]
• Optimizing Datapaths for Near Threshold ComputingMohammad Saber Golanbari, Mehdi Baradaran Tahoori. 69-72 [doi]
• Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability ModelsP. Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, J. Nunez, Javier Diaz-Fortuny, R. Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández. 73-76 [doi]
• Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)Sadik Iik, Fikret Basar Gencer, Mustafa Berke Yelten. 77-80 [doi]
• Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free NanopipelinesHector J. Quintero, Manuel Jimenez, Maria J. Avedillo, Juan Núñez. 81-84 [doi]
• A Memristive TaOx-Based Median Filter Design for Image Processing ApplicationAbubaker Sasi, Amirali Amirsoleimani, Majid Ahmadi, Arash Ahmadi. 85-88 [doi]
• Tunable Floating-Point for Embedded Machine Learning Algorithms ImplementationMarta Franceschi, Alberto Nannarelli, Maurizio Valle. 89-92 [doi]
• Approximate Fully Connected Neural Network GenerationTuba Ayhan, Mustafa Altun. 93-96 [doi]
• A Novel Multiple Membership Function Generator for Fuzzy Logic SystemsRamin Khayatzadeh, Mustafa Berke Yelten. 101-104 [doi]
• Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact ModelNihat Akkan, Mustafa Altun, Herman Sedef. 105-108 [doi]
• Three-Dimensional Modeling of Insulin Pen for Multi-Electrode Capacitive SensingMaria-Alexandra Paun, Catherine Dehollain. 113-116 [doi]
• Modeling and Simulation of Digital Phase-Locked Loop in SimulinkN. Parkalian, M. Robens, C. Grewinz, V. Christ, D. Liebau, P. Muralidharan, D. Nielinaer, U. Yegin, A. Zambanini, S. van Waasen. 121-9 [doi]
• Design Space Exploration of CMOS Cross-Coupled LC Oscillators via RF Circuit SynthesisEngin Afacan, Günhan Dündar. 125-128 [doi]
• Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular ApplicationsRicardo Martins 0003, Nuno Lourenço 0003, Nuno Horta, Jun Yin, Pui-In Mak, Rui P. Martins. 129-132 [doi]
• On the Exploration of Promising Analog IC Designs via Artificial Neural NetworksNuno Lourenço 0003, Joao Rosa, Ricardo Martins 0003, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta. 133-136 [doi]
• Expected Improvement-Based Optimization Approach for the Optimal Sizing of a CMOS Operational Transconductance AmplifierNawel Drira, Mouna Kotti, Mourad Fakhfakh, Patrick Siarry, Esteban Tlelo-Cuautle. 137-9 [doi]
• Lithography Hotspots Detection Using Deep LearningVadim Borisov, Jürgen Scheible. 145-148 [doi]
• Impact Rating of Layout Parasitics in Mixed-Signal Circuits: Finding a Needle in a HaystackGeorg Gläser, Martin Grabmann, Dirk Nuernbergk. 149-152 [doi]
• ToPoliNano & MagCAD: A Complete Framework for Design and Simulation of Digital Circuits Based on Emerging TechnologiesUmberto Garlando, Fabrizio Riente. 153-156 [doi]
• ReSeMBleD-Methods for Response Surface Model Behavioral DescriptionMaike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen. 157-160 [doi]
• Absynth: A Comprehensive Approach for Full Front to Back Analog Design AutomationAbhaya Chandra Kammara, Andreas König 0001. 165-168 [doi]
• Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC ApplicationsHsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh, Chien-Nan Jimmy Liu. 169-172 [doi]
• Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design AutomationGuan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su, Mark Po-Hung Lin. 173-176 [doi]
• Mismatch-Aware Placement of Device Arrays Using Genetic OptimizationIslam Nashaat, Inas Mohammed, Mohamed Dessouky, Hazem Said. 177-180 [doi]
• On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog LayoutsPo-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang. 181-184 [doi]
• Analytical Method for Ultra-Low Power UWB Low-Noise AmplifiersAhmed M. Saied, M. M. Abutaleb, Mohamed I. Eladawy, Hani Ragai. 189-192 [doi]
• Temperature Performance of Meander-Type Inductor in Silicon TechnologyAleksandar Pajkanovic, Goran M. Stojanovic. 193-196 [doi]
• Universal Model for Millimeter-Wave Integrated TransformersJohannes Herrmann, David Bierbuesse, Renato Negra. 197-200 [doi]
• On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient AnalysisCharalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. 201-204 [doi]
• Efficient Hotspot Thermal Simulation Via Low-Rank Model Order ReductionGeorge Floros, Nestor E. Evmorfopoulos, George Stamoulis. 205-208 [doi]
• A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU sDimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. 209-212 [doi]
• Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function DecompositionJennifer Freeley, Dmvtro Mishagli, Tom Brazil, Elena Blokhina. 213-9 [doi]
• Advanced Modeling Methodology for Expedient RF SoC Verification and Performance EstimationFabian Speicher, Jonas Meier, Christoph Beyerstedt, Ralf Wunderlich, Stefan Heinen. 221-224 [doi]
• Fast Converter Simulation Method Including Parasitic Nonlinear CapacitancesÉva Schmidt, Thomas Durbaum. 225-228 [doi]
• Pulse Compression for Ferrite Inductors Modeling in Moderate SaturationPietro Burrascano, Giulia Di Capua, Nicola Femia, Stefano Laureti, Marco Ricci. 229-232 [doi]
• Accurate Modeling of Inductors Working in Nonlinear Region in Switch-Mode Power Supplies with Different Load CurrentsAlberto Oliveri, Matteo Lodi, Marco Storace. 233-236 [doi]
• A Temperature Dependent Non-Linear Inductor Model for a DC/DC Boost ConverterD. Scire, S. Rosato, G. Lullo, G. Vitale. 237-9 [doi]
• Geometric form Factors-Based Power Transformers DesignGiulia Di Capua, Nicola Femia. 245-248 [doi]
• Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter ArchitecturesElisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen. 249-252 [doi]
• Analysis and Simulation of Chopper Stabilization Techniques Applied to Delta-Sigma ConvertersA. Catania, Andrea Ria, Simone Del Cesta, Massimo Piotto, Paolo Bruschi. 253-256 [doi]
• New Reconfigurable Universal SISO Biquad Filter Implemented by Advanced CMOS Active ElementsRoman Sotner, Lukas Langhammer, Ondrej Domansky, Jiri Petrzela, Jan Jerabek, Tomás Dostál. 257-260 [doi]
• System of Standard Approximations for Optimum Frequency Filter DesignKarel Hajek. 261-264 [doi]
• Design and Error Analysis of Inductance Multiplier via Symbolic AlgorithmsJiri Vavra, Dalibor Biolek, Zdenek Kolka. 265-268 [doi]
• A Low-Power, Bootstrapped Sample and Hold Circuit with Extended Input Ranged for Analog-to-Digital Converters in CMOS 0.18 μmAhmad Mohammadi, Mohammad Chahardori. 269-272 [doi]
• A Cell-Based Fractional-N Phase-Locked Loop CompilerCheng-En Lee, Shi-Yu Huang. 273-276 [doi]
• Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle ApplicationsWeiwei Shi 0001, An Pan. 277-280 [doi]
• Modeling of Reference Injection Based Low-Power All-Digital Phase-Locked Loop for Bluetooth Low-Energy Applications in Lab VIEWMuhammad Riaz ur Rehman, Nabeel Ahmad, Imran Ali, SeongJin Oh, Arash Hejazi, Kang-Yoon Lee. 281-283 [doi]
• SC Filter Optimization Performance by Hybrid Simplex AlgorithmJiri Nahlik, Jirí Hospodka, Ondrej Subrt. 285-288 [doi]
• A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous DetectorChee Young Lee, Chae Won Kim, Hyejin Im, Soo Youn Kim, Minkyu Song. 289-292 [doi]
• Kriging Metamodeling-Assisted Multi-Objective Optimization of CMOS Current ConveyorsMouna Kotti, Mourad Fakhfakh, Esteban Tlelo-Cuautle. 293-296 [doi]
• ®=-AMSVicente Y. Ponce-Hinestroza, Victor R. Gonzalez-Diaz. 301-304 [doi]
• Reconfiguring Passive Linear CircuitsCristian E. Onete, Maria Cristina C. Onete. 305-308 [doi]