Abstract is missing.
- SOC challenges in the terabit networks era Nick Ilyadis. 3 [doi]
- Future trends in PC computing and their implications to SoC Alexander D. Peleg. 4 [doi]
- Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore s law Kamran Eshraghian. 5-6 [doi]
- Energy-optimal signaling and ordering of bits for area-constrained interconnectsSharath Jayaprakash, Nihar R. Mahapatra. 9-12 [doi]
- A unified power measurement and management platform for pipelined MPSoC executionsSung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung. 13-16 [doi]
- Partitioned reuse cache for energy-efficient soft-error protection of functional unitsKaushal R. Gandhi, Nihar R. Mahapatra. 17-20 [doi]
- The role of interconnects in the performance scalability of multicore architecturesJiangjiang Liu, Nihar R. Mahapatra. 21-24 [doi]
- ILP-based scheme for timing variation-aware scheduling and resource bindingYibo Chen, Jin Ouyang, Yuan Xie. 27-30 [doi]
- Exploiting loop-level parallelism on multi-core architectures for the wimax physical layerYing Yi, Wei Han, Adam Major, Ahmet T. Erdogan, Tughrul Arslan. 31-34 [doi]
- Extensible software emulator for reconfigurable instruction cell based processorsMark Muir, Iain Lindsay, Tughrul Arslan, Ioannis Nousias, Sami Khawam, Mark Milward, Nazish Aslam, Adam Major. 35-40 [doi]
- MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processorsWei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan. 41-44 [doi]
- Pseudo-random clocking to enhance signal integritySelcuk Kose, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman. 47-50 [doi]
- Nanoscale on-chip decoupling capacitorsMikhail Popovich, Eby G. Friedman. 51-54 [doi]
- Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASICYuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall. 55-58 [doi]
- A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codesBo Fu, Paul Ampadu. 59-62 [doi]
- Fluidity concept for NoC: A congestion avoidance and relief routing schemeYing-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen. 65-70 [doi]
- Configurable error correction for multi-wire errors in switch-to-switch SOC linksQiaoyan Yu, Paul Ampadu. 71-74 [doi]
- Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architectureAzeez Sanusi, Nan Wang, Magdy A. Bayoumi. 75-78 [doi]
- Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoCPavel Ghosh, Arunabha Sen. 79-84 [doi]
- Composability in the time-triggered system-on-chip architectureHermann Kopetz, Christian El Salloum, Bernhard Huber, Roman Obermaisser, Christian Paukovits. 87-90 [doi]
- A systematic approach to synthesis of verification test-suites for modular SoC designsSudhakar Surendran, Rubin A. Parekhji, R. Govindarajan. 91-96 [doi]
- A 300-mV 36-muW multiphase dual digital clock output generator with self-calibrationMing-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang. 97-100 [doi]
- A resistance deviation-to-time interval converter for resistive sensorsJi-Man Park, Sung-Ik Jun. 101-104 [doi]
- Design methodolgy for HD Photo compression algorithm targeting a FPGASeth H. Groder, Kenneth W. Hsu. 105-108 [doi]
- Design of low flicker noise active CMOS mixerShao-Min Hsu, Yuyu Chang, John Choma Jr.. 109-112 [doi]
- 65NM sub-threshold 11T-SRAM for ultra low voltage applicationsFarshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao. 113-118 [doi]
- Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGAPhillip David Ferguson, Tughrul Arslan, Ahmet T. Erdogan, Andrew Parmley. 119-122 [doi]
- Novel start-up circuit with enhanced power-up characteristic for bandgap referencesTuan Vu Cao, Dag T. Wisland, Tor Sverre Lande, Farshad Moradi, Young-Hee Kim. 123-126 [doi]
- Unification of obstacle-avoiding rectilinear Steiner tree constructionIris Hui-Ru Jiang, Shung-Wei Lin, Yen-Ting Yu. 127-130 [doi]
- Analysis of retention time under multi-configuration on a DORGADaisaku Seto, Minoru Watanabe. 131-134 [doi]
- Performance evaluation of a FFT using adpative clockingHanni Bagnordi, Mabo Ito. 135-138 [doi]
- A comparator-based switched-capacitor integrator using a new charge control circuitFarhad Alibeygi Parsan, Ahmad Ayatollahi. 139-142 [doi]
- Area efficient delay-insensitive and differential current sensing on-chip interconnectEthiopia Nigussie, Juha Plosila, Jouni Isoaho. 143-146 [doi]
- Temperature measurement in Content Addressable Memory cells using bias-controlled VCOBasab Datta, Wayne P. Burleson. 147-150 [doi]
- A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devicesSyed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede. 151-154 [doi]
- A multi-mode sphere detector architecture for WLAN applicationsRamin Shariat-Yazdi, Tad Kwasniewski. 155-158 [doi]
- Slack redistribution in pipelined circuits for enhanced soft-error rate reductionSrivathsan Krishnamohan, Nihar R. Mahapatra. 159-162 [doi]
- Application development flow for on-chip distributed architecturesKhalid Latif, Moazzam Niazi, Hannu Tenhunen, Tiberiu Seceleanu, Sakir Sezer. 163-168 [doi]
- A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applicationsMd. Mahbub Reja, Kambiz K. Moez, Igor M. Filanovsky. 169-172 [doi]
- A robust ultra-low power asynchronous FIFO memory with self-adaptive power controlMu-Tien Chang, Po-Tsang Huang, Wei Hwang. 175-178 [doi]
- A low power and low area active clock deskewing technique for sub-90nm technologiesAshok Narasimhan, Ramalingam Sridhar. 179-182 [doi]
- A low power 32 nanometer CMOS digitally controlled oscillatorJun Zhao, Yong-Bin Kim. 183-186 [doi]
- Pseudo parallel architecture for AES with error correctionYi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan. 187-190 [doi]
- Implementing high definition video codec on TI DM6467 SOCJian Wang, Gang Hua. 193-196 [doi]
- A novel 5.46 mW H.264/AVC video stream parser ICMichelle Brown, Kenneth W. Hsu. 197-200 [doi]
- A low-power design of quantization for H.264 video coding standardMichael N. Michael, Kenneth W. Hsu. 201-204 [doi]
- Speed control for a hardware based H.264/AVC encoderChae-Eun Rhee, Jin-Su Jung, Hyuk-Jae Lee. 205-208 [doi]
- Power optimization for FinFET-based circuits using genetic algorithmsJin Ouyang, Yuan Xie. 211-214 [doi]
- In-situ self-aware adaptive power control system with multi-mode power gating networkWei-Chih Hsieh, Wei Hwang. 215-218 [doi]
- Supply voltage selection in Voltage Island based SoC designDipanjan Sengupta, Resve A. Saleh. 219-222 [doi]
- A multi-standard micro-programmable deblocking filter architecture and its application to VC-1 video decoderRicardo Citro, Miguel Guerrero, Jae-Beom Lee, Maria Pantoja. 225-228 [doi]
- Multi-standard sub-pixel interpolation architecture for video Motion EstimationLiang Lu, John V. McCanny, Sakir Sezer. 229-232 [doi]
- An efficient lossless embedded compression engine using compacted-FELICS algorithmYu-Yu Lee, Yu-Hsuan Lee, Tsung-Han Tsai. 233-236 [doi]
- Low-power floating bitline 8-T SRAM design with write assistant circuitsHao-I Yang, Ssu-Yun Lai, Wei Hwang. 239-242 [doi]
- A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologiesJawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 243-246 [doi]
- Low power 8T SRAM using 32nm independent gate FinFET technologyYoung Bok Kim, Yong-Bin Kim, Fabrizio Lombardi. 247-250 [doi]
- Failure analysis for ultra low power nano-CMOS SRAM under process variationsJawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 251-254 [doi]
- 1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technologyFuding Ge, Malay Trivedi, Brent Thomas, William Jiang, Hongjiang Song. 257-260 [doi]
- Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processesMartin Kosakowski, Reimund Wittmann, Werner Schardein. 261-266 [doi]
- A higher-order mismatch-shaping method for multi-bit Sigma-Delta ModulatorsAlexander Lavzin, Mücahit Kozak, Eby G. Friedman. 267-270 [doi]
- A low power sub-1 V CMOS voltage referenceSameer Somvanshi, Santhosh Kasavajjala. 271-276 [doi]
- Design space exploration for application specific FPGAS in system-on-a-chip designsMark Hammerquist, Roman L. Lysecky. 279-282 [doi]
- A framework of architectural synthesis for dynamically reconfigurable FPGAsTing Liu, Camel Tanougast, Serge Weber. 283-286 [doi]
- Reconfiguralbe multimedia accelerator for mobile systemsSamar Yazdani, Joel Cambonie, Bernard Pottier. 287-290 [doi]
- Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processorAbel G. Silva-Filho, Sidney M. L. Lima. 291-294 [doi]
- VLSI passive switched capacitor signal processing circuits: Circuit architecture, closed form modeling and applicationsHongjiang Song, Yan Song, Tai-Hua Chen. 297-300 [doi]
- A novel CMOS exponential approximation circuitMinglang Lin, Ahmet T. Erdogan, Tughrul Arslan, Adrian Stoica. 301-304 [doi]
- 3-D Heterogeneous SoC for detecting and filtering infected biological cellsV. K. Jain. 305-308 [doi]
- Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processingHongjiang Song. 309-312 [doi]
- Design of a baseband processor for software radio using FPGAsFerney Amaya-Fernandez, Jaime Velasco-Medina. 315-318 [doi]
- OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell ArrayXin Zhao, Ahmet T. Erdogan, Tughrul Arslan. 319-322 [doi]
- Reconfigurable flash A/D convertersCristian E. Onete. 323-326 [doi]
- Programmable all-digital adaptive deskewing and phase shiftingAlireza Kaviani, Tao Pi, Declan Kelly. 327-330 [doi]
- A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulatorHong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu. 333-336 [doi]
- A spread spectrum clock generator using digital modulation schemeChorng-Sii Hwang, Huan-Chun Li, Hen-Wai Tsao. 337-340 [doi]
- All digital time-to-digital converter using single delay-locked loopHong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin. 341-344 [doi]
- New low voltage, high PSRR, CMOS bandgap voltage referenceSeiede Fateme Ashrafi, Seied Mojtaba Atarodi, Mohammad Chahardori. 345-348 [doi]
- A timing methodology considering within-die clock skew variationsSavithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman Solovyev, Jacob A. Abraham. 351-356 [doi]
- X-clock routing based on pattern matchingChia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao. 357-360 [doi]
- An automated design method for chip power distributionDi Phan, Christopher J. Berry, Frank Malgioglio, Alan P. Wagstaff. 361-364 [doi]
- A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standardsYang Sun, Joseph R. Cavallaro. 367-370 [doi]
- High performance IP lookup circuit using DDR SDRAMXin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.. 371-374 [doi]
- Power/throughput/area efficient PIM-based reconfigurable array for parallel processingSohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello. 375-378 [doi]
- A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decodersSangho Yoon, Hanho Lee. 379-382 [doi]
- Design and verification of complex SoC with configurable, extensible processorsSteve Leibson, Grant Martin. 385 [doi]
- A new generation of C-base synthesis tool and domain-specific computingJason Cong. 386 [doi]
- Low power design under parameter variationsSwarup Bhunia, Kaushik Roy. 389-390 [doi]
- Real-time implementation of H.264 Video CodingIain E. Garden Richardson. 390 [doi]
- Asynchronous circuit design using Handshake SolutionsAd M. G. Peeters, Mark De Wit. 391-392 [doi]