Abstract is missing.
- Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit SynthesisAlmitra Pradhan, Ranga Vemuri. 1-20 [doi]
- A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based ClassifierSheng-Yu Peng, Paul E. Hasler, David V. Anderson. 1-20 [doi]
- Reconfigurable Acceleration with Binary Compatibility for General Purpose ProcessorsAntonio Carlos Schneider Beck, Luigi Carro. 1-16 [doi]
- QoS in Networks-on-Chip - Beyond Priority and Circuit Switching TechniquesAline Mello, Ney Calazans, Fernando Moraes. 1-22 [doi]
- The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and AlgorithmBassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz. 1-22 [doi]
- Use of Gray Decoding for Implementation of Symmetric FunctionsOsnat Keren, Ilya Levin, Radomir S. Stankovic. 1-16 [doi]
- Parametric Structure-Preserving Model Order ReductionJorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira. 1-20 [doi]
- ReCPU: a Parallel and Pipelined Architecture for Regular Expression MatchingMarco Paolieri, Ivano Bonesana, Marco D. Santambrogio. 1-20 [doi]
- SWORD: A SAT like Prover Using Word Level InformationRobert Wille, Görschwin Fey, Daniel Große, Daniel Große, Stephan Eggersglüß, Rolf Drechsler. 1-17 [doi]
- Compression-based SoC Test InfrastructuresJulien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. 1-15 [doi]
- Statistical and Numerical Approach for a Computer efficient circuit yield analysisLucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis. 1-24 [doi]
- First Order, Quasi-Static, SOI Charge Conserving Power Dissipation ModelSameer Sharma, L. G. Johnson. 1-23 [doi]
- Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS TechnologiesGustavo Neuberger, Gilson I. Wirth, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis. 1-16 [doi]
- An adaptive genetic algorithm for dynamically reconfigurable modules allocationVincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto. 1-18 [doi]
- System and Procesor Design Effort EstimationCyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau. 1-21 [doi]
- A new analytical approach of the impact of jitter on continuous time delta sigma convertersJulien Goulier, E. Andre, Marc Renaudin. 1-16 [doi]