Daesun Oh - researchr alias

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Viewing Publication 1 - 10 from 10

2010

Low-Complexity Switch Network for Reconfigurable LDPC DecodersDaesun Oh, Keshab K. Parhi. tvlsi, 18(1):85-94, 2010. [doi]

Min-Sum Decoder Architectures With Reduced Word Length for LDPC CodesDaesun Oh, Keshab K. Parhi. tcas, 57-I(1):105-115, 2010. [doi]

2009

Low Complexity Decoder Architecture for Low-Density Parity-Check CodesDaesun Oh, Keshab K. Parhi. vlsisp, 56(2-3):217-228, 2009. [doi]

2008

Optimally quantized offset min-sum algorithm for flexible LDPC decoderDaesun Oh, Keshab K. Parhi. acssc 2008: 1886-1891 [doi]

Nonuniformly quantized min-sum decoder architecture for low-density parity-check codesDaesun Oh, Keshab K. Parhi. glvlsi 2008: 451-456 [doi]

Area efficient controller design of barrel shifters for reconfigurable LDPC decodersDaesun Oh, Keshab K. Parhi. iscas 2008: 240-243 [doi]

2007

Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC CodesDaesun Oh, Keshab K. Parhi. iscas 2007: 2758-2761 [doi]

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check CodesDaesun Oh, Keshab K. Parhi. iscas 2007: 1855-1858 [doi]

2006

Low Complexity Design of High Speed Parallel Decision Feedback EqualizersDaesun Oh, Keshab K. Parhi. asap 2006: 118-124 [doi]

Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check CodesDaesun Oh, Keshab K. Parhi. sips 2006: 262-267 [doi]

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