Tomoharu Tanaka - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 12 from 12

2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memoryTomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung-Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo. isscc 2016: 142-144 [doi]

2010

A temperature compensation word-line voltage generator for multi-level cell NAND Flash memoriesToru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar. esscirc 2010: 106-109 [doi]

2009

2002

Circuit techniques for a 1.8-V-only NAND flash memoryToru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura. jssc, 37(1):84-89, 2002. [doi]

2001

A dual-page programming scheme for high-speed multigigabit-scale NAND flash memoriesKen Takeuchi, Tomoharu Tanaka. jssc, 36(5):744-751, 2001. [doi]

1999

th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memoriesKen Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui. jssc, 34(5):675-684, 1999. [doi]

1998

A multipage cell architecture for high-speed programming multilevel NAND flash memoriesKen Takeuchi, Tomoharu Tanaka, Toru Tanzawa. jssc, 33(8):1228-1238, 1998. [doi]

1997

1996

th select gate array architecture for multilevel NAND flash memoriesKen Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura. jssc, 31(4):602-609, 1996. [doi]

1994

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memoryTomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara. jssc, 29(11):1366-1373, November 1994. [doi]

Sign in or sign up to see more results.

runs on WebDSL