Abstract is missing.
- ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovationsSubhasish Mitra, Deming Chen. 1 [doi]
- ASP-DAC 2017 keynote speech I-1: Heterogeneous integration of X-tronics: Design automation and educationK. T. Tim Cheng. 2 [doi]
- ASP-DAC 2017 keynote speech I-2: Electronics for the human bodyJohn Rogers. 3 [doi]
- ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system designHiroto Yasuura. 4 [doi]
- W-band ultra-high data-rate 65nm CMOS wireless transceiverKorkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa. 5-6 [doi]
- An image sensor/processor 3D stacked module featuring ThruChip interfacesMasayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura. 7-8 [doi]
- 2 near-optimal symbol detector for spatial modulation MIMO systems in 0.18μm CMOSHye-Yeon Yoon, Gwang-Ho Lee, Tae-Hwan Kim. 9-10 [doi]
- A scalable time-domain biosensor array using logarithmic cyclic time-attenuation-based TDC for high-resolution and large-scale bio-imagingKei Ikeda, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu. 11-12 [doi]
- An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generationDongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. 13-14 [doi]
- A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog componentsYuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta. 15-16 [doi]
- Non-binary cyclic ADC with correlated level shifting techniqueHiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta. 17-18 [doi]
- A current-integration-based CMOS amperometric sensor with 1.2 μm × 2.05 μm electroless-plated microelectrode array for high-sensitivity bacteria countingKohei Gamo, Kazuo Nakazato, Kiichi Niitsu. 19-20 [doi]
- A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOSMinkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo. 21-22 [doi]
- A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readoutXiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada. 23-24 [doi]
- Design of an energy-autonomous bio-sensing system using a biofuel cell and 0.19V 53μW integrated supply-sensing sensor with a supply-insensitive temperature sensor and inductive-coupling transmitterAtsuki Kobayashi, Kei Ikeda, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato, Kiichi Niitsu. 25-26 [doi]
- A 13.56MHz CMOS active diode full-wave rectifier achieving ZVS with voltage-time-conversion delay-locked loop for wireless power transmissionKeita Yogosawa, Hideki Shinohara, Kousuke Miyaji. 27-28 [doi]
- CMOS-on-quartz pulse generator for low power applicationsParit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada. 29-30 [doi]
- A 13.56 MHz on/off delay-compensated fully-integrated active rectifier for biomedical wireless power transfer systemsLin Cheng, Wing-Hung Ki, Tak-Sang Yim. 31-32 [doi]
- A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applicationsLin Cheng, Wing-Hung Ki, Chi-Ying Tsui. 33-34 [doi]
- Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systemsHiroki Asano, Tetsuya Hirose, T. Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa. 35-36 [doi]
- A 19-μA metabolic equivalents monitoring SoC using adaptive samplingMio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori. 37-38 [doi]
- An FPGA-compatible PLL-based sensor against fault injection attackWei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata. 39-40 [doi]
- Variability mapping at runtime using the PAnDA multi-reconfigurable architectureSimon J. Bale, James Alfred Walker, Martin A. Trefzer, Andy M. Tyrrell. 41-42 [doi]
- Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting techniqueYosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Dong Ruibing, Shiro Dosho, Noboru Ishihara, Kazuya Masu. 43-44 [doi]
- AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCsBiruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco. 45-50 [doi]
- Feature extraction from design documents to enable rule learning for improving assertion coverageKuo-Kai Hsieh, Sebastian Siatkowski, Li-C. Wang, Wen Chen, Jayanta Bhadra. 51-56 [doi]
- Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPsKenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler. 57-62 [doi]
- Efficient floating point precision tuning for approximate computingNhut-Minh Ho, Elavarasi Manogaran, Weng-Fai Wong, Asha Anoosheh. 63-68 [doi]
- Area-constrained technology mapping for in-memory computing using ReRAM devicesDebjyoti Bhattacharjee, Arvind Easwaran, Anupam Chattopadhyay. 69-74 [doi]
- Tessellating memory space for parallel accessJuan Escobedo, Mingjie Lin. 75-80 [doi]
- Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagationYoichi Tomioka, Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima. 81-86 [doi]
- Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instabilityShanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao. 87-92 [doi]
- Efficient circuit failure probability calculation along product lifetime considering device agingHiromitsu Awano, Masayuki Hiromoto, Takashi Sato. 93-98 [doi]
- Low-power image recognition challengeKent Gauen, Rohit Rangan, Anup Mohan, Yung-Hsiang Lu, Wei Liu, Alexander C. Berg. 99-104 [doi]
- CNN-based object detection solutions for embedded heterogeneous multicore SoCsCheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li. 105-110 [doi]
- Low-power neuromorphic speech recognition engine with coarse-grain sparsityShunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo. 111-114 [doi]
- Towards acceleration of deep convolutional neural networks using stochastic computingJi Li, Ao Ren, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang. 115-120 [doi]
- Enabling fast preemption via Dual-Kernel support on GPUsLi-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang. 121-126 [doi]
- Efficient mapping of CDFG onto coarse-grained reconfigurable array architecturesSatyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini. 127-132 [doi]
- Timing window wiper: A new scheme for reducing refresh power of DRAMHo Hyun Shin, Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim, Eui-Young Chung. 133-138 [doi]
- On efficient message passing in energy harvesting based distributed systemYe Tian, Qiang Xu, Jason Xue. 139-144 [doi]
- Fast-extract with cube hashingBruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis. 145-150 [doi]
- A novel basis for logic rewritingWinston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 151-156 [doi]
- Multi-level logic benchmarks: An exactness studyLuca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 157-162 [doi]
- Approximate logic synthesis for FPGA by wire removal and local function changeYi Wu, Chuyu Shen, Yi Jia, Weikang Qian. 163-169 [doi]
- Guiding template-aware routing considering redundant via insertion for directed self-assemblyKun-Lin Lin, Shao-Yun Fang. 170-175 [doi]
- Workload-aware static aging monitoring of timing-critical flip-flopsArunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 176-181 [doi]
- Enhancing robustness of sequential circuits using application-specific knowledge and formal methodsSebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler. 182-187 [doi]
- WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based CachesSina Asadi, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi. 188-193 [doi]
- Securing the hardware of cyber-physical systemsFrancesco Regazzoni, Ilia Polian. 194-199 [doi]
- Cross-domain security of cyber-physical systemsSujit Rokka Chhetri, Jiang Wan, Mohammad Abdullah Al Faruque. 200-205 [doi]
- A systematic security analysis of real-time cyber-physical systemsArvind Easwaran, Anupam Chattopadhyay, Shivam Bhasin. 206-213 [doi]
- Automated generation of dynamic binary translators for instruction set simulationKatsumi Okuda, Minoru Yoshida, Haruhiko Takeyama, Minoru Nakamura. 214-219 [doi]
- Loop aware IR-level annotation framework for performance estimation in native simulationOmayma Matoussi, Frédéric Petrot. 220-225 [doi]
- Hybrid analysis of SystemC models for fast and accurate parallel simulationTim Schmidt, Guantao Liu, Rainer Dömer. 226-231 [doi]
- Virtual prototyping of smart systems through automatic abstraction and mixed-signal schedulingMichele Lora, Enrico Fraccaroli, Franco Fummi. 232-237 [doi]
- Efficient parallel verification of Galois field multipliersCunxi Yu, Maciej J. Ciesielski. 238-243 [doi]
- Property mining using dynamic dependency graphsJan Malburg, Tino Flenker, Görschwin Fey. 244-250 [doi]
- CEGAR-based EF synthesis of Boolean functions with an application to circuit rectificationHeinz Riener, Rüdiger Ehlers, Görschwin Fey. 251-256 [doi]
- An extensible perceptron framework for revision RTL debug automationJohn Adler, Ryan Berryhill, Andreas G. Veneris. 257-262 [doi]
- Algorithm for synthesis and exploration of clock spinesYoungchan Kim, Taewhan Kim. 263-268 [doi]
- Yield-driven redundant power bump assignment for power network robustnessYu-Min Lee, Chi-Han Lee, Yan-Cheng Zhu. 269-274 [doi]
- A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCsMeng Liu, Matthias Becker, Moris Behnam, Thomas Nolte. 275-282 [doi]
- An efficient homotopy-based Poincaré-Lindstedt method for the periodic steady-state analysis of nonlinear autonomous oscillatorsZhongming Chen, Kim Batselier, Haotian Liu, Ngai Wong. 283-288 [doi]
- ASP-DAC 2017 keynote speech II: Emerging medical technologies for interfacing the brain: From deep brain stimulation to brain computer interfacesNapoleon Torres-Martinez. 289 [doi]
- Smart electrode - toward a retinal stimulator with the large number of electrodesJun Ohta. 290 [doi]
- Strategic circuits for neuromodulation of the visual systemGregg J. Suaning. 291-294 [doi]
- Design considerations and clinical applications of closed-loop neural disorder control SoCsChung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw. 295-298 [doi]
- Emerging technologies for biomedical applications: Artificial vision systems and brain machine interfaceMasaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez. 299 [doi]
- A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical ringsMarta Ortín-Obón, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi. 300-305 [doi]
- Islands of heaters: A novel thermal management framework for photonic NoCsDharanidhar Dang, Sai Vineel Reddy Chittamuru, Rabi N. Mahapatra, Sudeep Pasricha. 306-311 [doi]
- Energy-aware loops mapping on multi-vdd CGRAs without performance degradationJiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei. 312-317 [doi]
- Algorithm accelerations for luminescent solar concentrator-enhanced reconfigurable onboard photovoltaic systemCaiwen Ding, Ji Li, Weiwei Zheng, Naehyuck Chang, Xue Lin, Yanzhi Wang. 318-323 [doi]
- Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristicsZuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Yingnan Cui. 324-329 [doi]
- Ensuring system security through proximity based authenticationJoshua Marxen, Alex Orailoglu. 330-335 [doi]
- VOLtA: Voltage over-scaling based lightweight authentication for IoT applicationsMd Tanvir Arafin, Mingze Gao, Gang Qu. 336-341 [doi]
- Security analysis of Anti-SATMuhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran. 342-347 [doi]
- Exploiting accelerated aging effect for on-line configurability and hardware trackingYang You, Jie Gu. 348-353 [doi]
- SGXCrypter: IP protection for portable executables using Intel's SGX technologyDimitrios Tychalas, Nektarios Georgios Tsoutsos, Michail Maniatakos. 354-359 [doi]
- Network flow based cut redistribution and insertion for advanced 1D layout designYe Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng. 360-365 [doi]
- An efficient algorithm for stencil planning and optimization in E-beam lithographyJiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng. 366-371 [doi]
- Flexible interconnect in 2.5D ICs to minimize the interposer's metal layersDaniel P. Seemuth, Azadeh Davoodi, Katherine Morrow. 372-377 [doi]
- Optimizing DSA-MP decomposition and redundant via insertion with dummy viasChung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak. 378-383 [doi]
- Design of multiple fanout clock distribution network for rapid single flux quantum technologyNaveen Katam, Alireza Shafaei, Massoud Pedram. 384-389 [doi]
- A novel data format for approximate arithmetic computingMingze Gao, Qian Wang, Akshaya S. Kankanhalli-Nagendra, Gang Qu. 390-395 [doi]
- ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memoryYibin Tang, Ying Wang, Huawei Li, Xiaowei Li. 396-401 [doi]
- ApproxEye: Enabling approximate computation reuse for microrobotic computer visionXin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li. 402-407 [doi]
- On resilient task allocation and scheduling with uncertain quality checkersQian Zhang, Ting Wang, Qiang Xu. 408-413 [doi]
- An artificial neural network approach for screening test escapesFan Lin, Kwang-Ting Cheng. 414-419 [doi]
- Processor shield for L1 data cache software-based on-line self-testingChing-Wen Lin, Chung-Ho Chen. 420-425 [doi]
- Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniquesTzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao. 426-431 [doi]
- A local reconfiguration based scalable fault tolerant many-processor arraySoumya Banerjee, Wenjing Rao. 432-437 [doi]
- Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuitsJai-Ming Lin, Bo-Heng Yu, Li-Yen Chang. 438-443 [doi]
- Floorplan and placement methodology for improved energy reduction in stacked power-domain designKristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez. 444-449 [doi]
- An effective legalization algorithm for mixed-cell-height standard cellsChao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan. 450-455 [doi]
- Delay-driven layer assignment for advanced technology nodesSzu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang. 456-462 [doi]
- STEAM: Spline-based tables for efficient and accurate device modellingArchit Gupta, Tianshi Wang, Ahmet Mahmutoglu Gokcen, Jaijeet Roychowdhury. 463-468 [doi]
- A time domain behavioral model for oscillators considering flicker noiseHui Zhang, Bo Wang. 469-474 [doi]
- Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuitsTuotian Liao, Lihong Zhang. 475-480 [doi]
- High-speed stochastic circuits using synchronous analog pulsesM. Hassan Najafi, David J. Lilja. 481-487 [doi]
- Throughput optimization for streaming applications on CPU-FPGA heterogeneous systemsXuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong. 488-493 [doi]
- Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systemsLei Yang 0018, Weichen Liu, Nan Guan, Mengquan Li, Peng Chen, Edwin Hsing-Mean Sha. 494-499 [doi]
- Non-intrusive dynamic profiler for multicore embedded systemsSudarshan Sargur, Roman Lysecky. 500-505 [doi]
- Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chipsXiaokun Yang, Wujie Wen. 506-511 [doi]
- Piracy prevention of digital microfluidic biochipsChing-Wei Hsieh, Zipeng Li, Tsung-Yi Ho. 512-517 [doi]
- On reliability hardening in cyber-physical digital-microfluidic biochipsGuan-Ruei Lu, Guan-Ming Huang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen. 518-523 [doi]
- Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochipsQin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai. 524-529 [doi]
- Close-to-optimal placement and routing for continuous-flow microfluidic biochipsAndreas Grimmer, Qin Wang, Hailong Yao, Tsung-Yi Ho, Robert Wille. 530-535 [doi]
- ASP-DAC 2017 keynote speech III: All-programmable FPGAs: More powerful devices require more powerful toolsSteve Trimberger. 536 [doi]
- Containing guardbandsHussam Amrouch, Jörg Henkel. 537-542 [doi]
- Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approachYu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang. 543-548 [doi]
- Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realizationWei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou. 549-553 [doi]
- CN-SIM: A cycle-accurate full system power delivery noise simulatorKassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi. 554-559 [doi]
- Improving LDPC performance via asymmetric sensing level placement on flash memoryQiao Li, Liang Shi, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 560-565 [doi]
- A flash scheduling strategy for current capping in multi-power-mode SSDsLi-Pin Chang, Chia-Hsiang Cheng, Kai-Hsiang Lin. 566-571 [doi]
- Temperature-aware data allocation strategy for 3D charge-trap flash memoryYi Wang, Mingxu Zhang, Jing Yang. 572-577 [doi]
- Scalable frequent-pattern mining on nonvolatile memoriesYi Lin, Po-Chun Huang, Duo Liu, Liang Liang. 578-583 [doi]
- KVFTL: Optimization of storage space utilization for key-value-specific flash storage devicesYen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen, Hsin-Wen Wei, Wei Kuan Shih. 584-590 [doi]
- Trojan localization using symbolic algebraFarimah Farahmandi, Yuanwen Huang, Prabhat Mishra. 591-597 [doi]
- Detecting hardware Trojans in unspecified functionality through solving satisfiability problemsNicole Fern, Ismail San, Kwang-Ting (Tim) Cheng. 598-504 [doi]
- Routing perturbation for enhanced security in split manufacturingYujie Wang, Pu Chen, Jiang Hu, Jeyavijayan J. V. Rajendran. 605-510 [doi]
- MUTARCH: Architectural diversity for FPGA device and IP securityRobert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia. 611-616 [doi]
- Security vulnerability analysis of design-for-test exploits for asset protection in SoCsGustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor. 617-622 [doi]
- Towards scalable and efficient GPU-enabled slicing acceleration in continuous 3D printingAosen Wang, Chi Zhou, Zhanpeng Jin, Wenyao Xu. 623-628 [doi]
- FPGA-based accelerator for long short-term memory recurrent neural networksYijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong. 629-634 [doi]
- Fine-grained accelerators for sparse machine learning workloadsAsit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr. 635-640 [doi]
- High throughput hardware architecture for accurate semi-global matchingYan Li, Chen Yang, Wei Zhong, Zhiwei Li, Song Chen. 641-646 [doi]
- A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applicationsChenchen Liu, Qing Yang, Chi Zhang, Hao Jiang, Qing Wu, Hai Helen Li. 647-652 [doi]
- An adaptive on-line CPU-GPU governor for games on mobile devicesPo-Kai Chuang, Ya-Shu Chen, Po-Hao Huang. 653-658 [doi]
- A static scheduling approach to enable safety-critical OpenMP applicationsAlessandra Melani, Maria A. Serrano, Marko Bertogna, Isabella Cerutti, Eduardo Quiñones, Giorgio C. Buttazzo. 659-665 [doi]
- Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCsChia-Ling Chen, Yen-Hao Chen, TingTing Hwang. 666-671 [doi]
- Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPUAmir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis. 672-677 [doi]
- Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processorsKaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, Yongpan Liu, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan. 678-683 [doi]
- Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore systemZhe Wang, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Haoran Li, Peng Yang, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen. 684-689 [doi]
- BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniquesJingyang Zhu, Zhiliang Qian, Chi-Ying Tsui. 690-695 [doi]
- Scalable stochastic-computing accelerator for convolutional neural networksHyeon Uk Sim, Dong Nguyen, Jongeun Lee, Kiyoung Choi. 696-701 [doi]
- Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochipsVarsha Agarwal, Ananya Singla, Mahammad Samiuddin, Sudip Roy 0001, Tsung-Yi Ho, Indranil Sengupta, Bhargab B. Bhattacharya. 702-707 [doi]
- Exact routing for micro-electrode-dot-array digital microfluidic biochipsOliver Keszocze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler. 708-713 [doi]
- Majority logic circuits optimisation by node mergingChun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu. 714-719 [doi]
- A statistical STT-RAM retention model for fast memory subsystem designsZihao Liu, Wujie Wen, Lei Jiang, Yier Jin, Gang Quan. 720-725 [doi]
- DLPS: Dynamic laser power scaling for optical Network-on-ChipFan Lan, Rui Wu, Chong Zhang, Yun Pan, Kwang-Ting (Tim) Cheng. 726-731 [doi]
- Adaptive load distribution in mixed-critical Networks-on-ChipAdam Kostrzewa, Sebastian Tobuschat, Leonardo Ecco, Rolf Ernst. 732-737 [doi]
- BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systemsShiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li. 738-743 [doi]
- Using segmentation to improve schedulability of RRA-based NoCs with mixed trafficMeng Liu, Matthias Becker, Moris Behnam, Thomas Nolte. 744-750 [doi]
- Building energy-efficient multi-level cell STT-RAM caches with data compressionLiu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie. 751-756 [doi]
- MPIM: Multi-purpose in-memory processing using configurable resistive memoryMohsen Imani, Yeseong Kim, Tajana Rosing. 757-763 [doi]
- Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid bufferChuhan Min, Jie Guo, Hai Li, Yiran Chen. 764-769 [doi]
- Locality-aware bank partitioning for shared DRAM MPSoCsYangguo Liu, Junlin Lu, Dong Tong, Xu Cheng. 770-775 [doi]
- Classification accuracy improvement for neuromorphic computing systems with one-level precision synapsesYandan Wang, Wei Wen, Linghao Song, Hai Helen Li. 776-781 [doi]
- Binary convolutional neural network on RRAMTianqi Tang, Lixue Xia, Boxun Li, Yu Wang 0002, Huazhong Yang. 782-787 [doi]
- Algorithm-hardware co-optimization of the memristor-based framework for solving SOCP and homogeneous QCQP problemsAo Ren, Sijia Liu, Ruizhe Cai, Wujie Wen, Pramod K. Varshney, Yanzhi Wang. 788-793 [doi]
- Computation-oriented fault-tolerance schemes for RRAM computing systemsWenqin Huangfu, Lixue Xia, Ming Cheng, Xiling Yin, Tianqi Tang, Boxun Li, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, Huazhong Yang. 794-799 [doi]