Table of Contents

• Uniform area timing-driven circuit implementationDimitrios Karayiannis, Spyros Tragoudas. 2-7 [doi]
• Optimization using implicit techniques for industrial designsFrank Poirot, Gerard Tarroux, Ramine Roane. 8-14 [doi]
• Optimal technology mapping for single output cellsUwe Hinsberger, Reiner Kolla. 14 [doi]
• A Differential Model Approach To Analog Design AutomationD. J. Klein, M. L. Manwaring. 22-27 [doi]
• A new approach for modeling and optimization of analog systemsE. Penn, L. Schelovanov. 28-32 [doi]
• A scalable analog architecture for neural networks with on-chip learning and refreshingBassem A. Alhalabi, Magdy A. Bayoumi. 33 [doi]
• Bus minimization and scheduling of multi-chip systemsMichael Sheliga, Edwin Hsing-Mean Sha. 40-45 [doi]
• Thumbnail rectilinear Steiner treesJoseph L. Ganley, James P. Cohoon. 46-49 [doi]
• A two-stage simulated annealing methodologyJames M. Varanelli, James P. Cohoon. 50-53 [doi]
• Optimizing wiring space in slicing floorplansJ. T. Mowchenko, Y. Yang. 54 [doi]
• Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networksEnrico Macii, Massimo Poncino. 60-65 [doi]
• Design and analysis of a low-power energy-recovery adderNestoras Tzartzanis, William C. Athas. 66-69 [doi]
• Coding a terminated bus for low powerMircea R. Stan, Wayne P. Burleson. 70-73 [doi]
• Circuit/architecture for low-power high-performance 32-bit adderI. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan. 74 [doi]
• Symbolic execution of data pathsChuck Monahan, Forrest Brewer. 80-85 [doi]
• Specification and synthesis of bounded indirectionM. Esen Tuna, Kamlesh Rath, Steven D. Johnson. 86-89 [doi]
• Synthesis of SEU-tolerant ASICs using concurrent error correctionHarry Hollander, Bradley S. Carlson, Toby D. Bennett. 90-93 [doi]
• Scheduling conditional data-flow graphs with resource sharingJayesh Siddhiwala, Liang-Fang Chao. 94 [doi]
• Automated verification of temporal properties specified as state machines in VHDLYatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell. 100-105 [doi]
• Partitioning transition relations efficiently and automaticallyZijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin. 106-111 [doi]
• Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functionsEnrico Macii, Massimo Poncino. 112 [doi]
• An efficient building block layout methodology for compact placementNikolaos G. Bourbakis, Mohammad Mortazavi. 118-123 [doi]
• Performance driven standard-cell placement using the genetic algorithmHabib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten. 124-127 [doi]
• An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell PlacementJin-Tai Yan. 128-131 [doi]
• Priority driven channel pin assignmentInes Peters, Paul Molitor. 132 [doi]
• A systolic algorithm and architecture for image thinningN. Ranganathan, K. B. Doreswamy. 138-143 [doi]
• Analyzing and verifying locally clocked circuits with the concurrency workbenchGarth Baulch, David Hemmendinger, Cherrice Traver. 144-147 [doi]
• Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAsJae-Tack Yoo, Erik Brunvand, Kent F. Smith. 148-151 [doi]
• A local clocking approach for self-timed datapath designsSeokjin Kim, Ramalingam Sridhar. 152 [doi]
• A soft computing approach to hardware software codesignVincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo. 158-163 [doi]
• Technology mapping algorithms for sequential circuits using look-up table based FPGASStanley Habib, Quan Xu. 164-167 [doi]
• Modeling of communication protocols in VHDLAli Assi, Bozena Kaminska. 168-171 [doi]
• Using EDIF for software generationM. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward. 172 [doi]
• A protocol extraction strategy for control point insertion in design for test of transition signaling circuitsHon F. Li, P. N. Lam. 178-183 [doi]
• Statistical estimation of delay fault detectabilities and fault gradingZaifu Zhang, Robert D. McLeod, Gregory E. Bridges. 184-187 [doi]
• Test application time reduction for scan based sequential circuitsHao Zheng, Kewal K. Saluja, Rajiv Jain. 188-191 [doi]
• Pseudo-random behavioral ATPGAnne-lise Courbis, Jean François Santucci. 192 [doi]
• Fast algorithm for performance-oriented Steiner routingManjit Borah, Robert Michael Owens, Mary Jane Irwin. 198-203 [doi]
• On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routingAnthony D. Johnson. 204-207 [doi]
• OPRON: a new approach to planar OTC routingSrinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, A. Sureka. 208-212 [doi]
• Parallel hierarchical global routing for general cell layoutSanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman. 212 [doi]
• Improving self-timed pipeline ring performance through the addition of buffer loopsHai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha. 218-223 [doi]
• Scan testing of asynchronous sequential circuitsO. A. Petlin, Stephen B. Furber. 224-229 [doi]
• A new look at the conditions for the synthesis of speed-independent circuitsEnric Pastor, Jordi Cortadella, Oriol Roig. 230 [doi]
• Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RITL. F. Fuller, C. Kraaijenvanger. 238-241 [doi]
• Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self testHardy J. Pottinger, Chien-Yuh Lin. 242-245 [doi]
• Linking fabrication and parametric testing to VLSI design coursesRobert Pearson. 246-249 [doi]
• A personal computer based VLSI design curriculumWallace B. Leigh. 250 [doi]
• A scalable shared buffer ATM switch architectureA. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi. 256-261 [doi]
• ATM burst traffic generatorPong P. Chu. 262-265 [doi]
• A universal formalization of the effects of threshold voltages for discrete switch-level circuit modelsW. H. F. J. Körver. 266 [doi]