Abstract is missing.
- On the use of hierarchy in timing verification with statically sensitizable pathsP. Johannes, Luc J. M. Claesen, Hugo De Man. 4-8 [doi]
- A design for concurrent error detections in FPLAsTsin-Yuan Chang, Jean-Bean Hsu, Cheng Chi Wang, Yu Shen Lin. 9-15 [doi]
- A chip solution to hierarchical and boundary-scan compatible board level BISTOliver F. Haberl, Thomas Kropf. 16-21 [doi]
- Examining routing solutionsS. Bapat, James P. Cohoon, Patrick L. Heck, A. Ju, L. J. Randall. 24-29 [doi]
- The parallel complexity of minimizing column conflictsJohn E. Savage, Markus G. Wloka. 30-34 [doi]
- Performance driven placement with global routing for macro cellsAndrew Lim, Yeow Meng Chee, Ching-Ting Wu. 35-41 [doi]
- A heuristic for data path synthesis using multiport memoriesImtiaz Ahmad, C. Y. Roger Chen. 44-51 [doi]
- Models for bit-true simulation and high-level synthesis of DSP applicationsMarc Pauwels, Dirk Lanneer, Francky Catthoor, Gert Goossens, Hugo De Man. 52-59 [doi]
- High performance data-path synthesis via communication metricsAndrew Seawright, Forrest Brewer. 60-67 [doi]
- Cutwidth approximation in linear timeHeather Booth, Rajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi. 70-73 [doi]
- Quadtree interconnection network layoutSourav Bhattacharya, Shekhar H. Kirani, Wei-Tek Tsai. 74-81 [doi]
- Interactive optimal channel router for critical netsAntonije D. Jovanovic, Yee Yolk Yeng. 84-90 [doi]
- Two-layer via-free routing in channels and switchboxesKuo-Feng Liao. 91-94 [doi]
- A new conflict resolving switchbox routerTae Won Cho, Sam S. Pyo, J. Robert Heath. 95-102 [doi]
- An asynchronous multiplierBrenda Luderman, Alexander Albicki. 104-108 [doi]
- Self-timed pipeline with adderJohn Compton, Alexander Albicki. 109-113 [doi]
- VLSI implementation of controllers for communication protocols from their Petri net modelsAsjad M. T. Khan, Sadiq M. Sait, Gerhard F. Beckhoff. 114-121 [doi]
- An alternative algorithm for high speed multiplication and addition using growing techniqueReza Hashemian. 124-129 [doi]
- A systematic approach for designing systolic arraysChang N. Zhang, Alen George Law, Ali Rezazadeh. 130-137 [doi]
- A new algorithm for signal flow determination in CMOS VLSIA. R. Baba-Ali. 138-141 [doi]
- Routing in a rectangle with k-ary overlapJon Hamkins, Donna J. Brown. 144-151 [doi]
- An algorithm for embedding a class of non-even routing problems in even routing problemsDee Parks, Miroslaw Truszczynski. 152-158 [doi]
- A signed hypergraph model of constrained via minimizationC.-J. Richard Shi. 159-166 [doi]
- Interface constrained processor specification and schedulingJack Greenbaum, Forrest Brewer. 168-175 [doi]
- On the detection and elimination of superfluous level-sensitive latchesGlenn Jennings. 176-182 [doi]
- Axiomatic semantics of a hardware specification languageXin Hua, Hantao Zhang. 183-190 [doi]
- T-algorithm-based logic simulation on distributed systemsS. Sundaram, Lalit M. Patnaik. 191-195 [doi]
- Clock tree regenerationJan-Ming Ho, Ren-Song Tsay. 198-203 [doi]
- The Steiner tree problem with minimum number of vertices in graphsKia Makki, Niki Pissinou. 204-206 [doi]
- Optimum Steiner tree generationForbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave. 207-212 [doi]